Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
1995-05-30
2001-09-04
Fahmy, Wael (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S396000, C257S397000, C257S398000, C257S399000, C257S400000, C257S401000, C257S512000, C257S521000, C257S647000, C257S513000, C257S755000, C257S760000, C257S774000
Reexamination Certificate
active
06285073
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor devices, and more specifically to a contact structure in an integrated circuit and its method of formation.
BACKGROUND OF THE INVENTION
The semiconductor industry continually strives to increase device performance and device density by reducing device dimensions. More specifically, in the past the area on a chip occupied by active devices, known as the active area, and area on a chip used to isolate active devices, known as the isolation area, have been reduced in order to achieve higher device packing densities and improved device performance. This continuing reduction in device dimensions, however, has also begun to adversely effect the performance and the reliability of these scaled devices. This is because device parasitics, such as contact resistance, begin to limit the performance and reliability of these devices as they are scaled.
One technique which has been proposed for reducing the area required to isolate active devices in high density integrated circuits is trench isolation. With trench isolation, field oxide encroachment into the surrounding active area is eliminated, and therefore the area required for both device isolation and active devices can be simultaneously reduced. Unfortunately, reducing the active area of a device also reduces the area available to make contact to that device. As a result, devices having submicron design rules have small contact areas, and therefore the parasitic resistance associated with contacting these submicron devices can be high because contact resistance is dependent on contact area. Moreover, at submicron dimensions the parasitic resistance associated with these small contacts becomes high enough to limit the speed at which integrated circuits perform and to degrade device reliability. Accordingly, a need exists for a contact structure that allows high density integrated circuits to be fabricated with low contact resistance.
SUMMARY OF THE INVENTION
The previously mentioned problems with existing contact structures are overcome by the present invention. In one embodiment of the invention a contact structure in an integrated circuit has a semiconductor substrate with a trench isolation region formed therein, and trench isolation region has a trench sidewall. It has a doped region lying within the semiconductor substrate and the doped region abuts the trench sidewall. It has a conductive member. The conductive member having a first portion electrically coupled to the doped region along the trench sidewall. Other aspects of the invention also involve methods for making the contact structure in an integrated circuit. These and other features, and advantages, will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. It is important to point out that the illustrations may not necessarily be drawn to scale, and that there may be other embodiments of the present invention that are not specifically illustrated.
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Cooper Kent J.
Roth Scott S.
Fahmy Wael
Warren Matthew E.
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