Contact in planar NROM technology

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays

Reexamination Certificate

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Details

C257S315000, C257S410000, C257S322000, C257S324000, C257S774000, C257SE29064

Reexamination Certificate

active

08053812

ABSTRACT:
A method for fabricating a non-volatile memory array includes placing contacts over bit lines in a self-aligned manner. The placing includes forming self-aligned contact holes bounded by a second insulating material resistant to the removal of a first insulating material previously deposited over the bit lines, and depositing contact material, wherein the second insulating material blocks effusion of the contact material beyond the contact holes. The distance between neighboring bit lines in the array does not include a margin for contact misalignment.

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