Contact for integrated circuits

Fishing – trapping – and vermin destroying

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Details

357 55, 357 71, 357 73, 437180, 437235, 437978, 437982, H01L 2934, H01L 2144

Patent

active

051172739

ABSTRACT:
A method for forming a contact in a semiconductor integrated circuit includes the formation of a conformal oxide layer over the device followed by formation of a doped glass layer. The integrated circuit is heated to cause the glass layer to reflow, improving planarity of the circuit. A second conformal oxide layer is then formed, and contact vias are cut through the three part interlevel dielectric layer. Side walls are then formed in the via by depositing a third conformal layer, and anisotropically etching such layer. This isolates the doped reflowable glass layer from the via. Metal interconnect can then be deposited and defined, forming a contact in the via.

REFERENCES:
patent: 4485393 (1984-11-01), Kumamaru et al.
patent: 4962414 (1990-10-01), Liou et al.
patent: 4972251 (1990-11-01), Lehrer

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