Contact etching utilizing partially recessed hard mask

Details Contact etching utilizing partially recessed hard mask Contact etching utilizing partially recessed hard mask

2006-11-14

2006-11-14

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C257S758000, C257S774000, C257S750000

Reexamination Certificate

active

07135783

ABSTRACT:
A method for forming contact holes using a partially recessed hard mask. A substrate with a device region and an alignment region having an opening therein, acting as an alignment mark, is provided. A dielectric layer is formed overlying the substrate and fills the opening. A polysilicon layer is formed on the dielectric layer, with over the opening on the alignment region comprising a recessed region and on the device region comprising a plurality of holes therein to expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form contact holes therein.

REFERENCES:
patent: 2003/0098509 (2003-05-01), Kamiya et al.
patent: 2003/0109113 (2003-06-01), Wen et al.

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