Contact etching utilizing multi-layer hard mask

Details Contact etching utilizing multi-layer hard mask Contact etching utilizing multi-layer hard mask

2006-01-17

2006-01-17

Thomas, Tom (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S750000, C257S751000, C257S756000, C257S797000

Reexamination Certificate

active

06987322

ABSTRACT:
A method for forming contact holes using a multi-layer hard mask. A substrate with a device region and an alignment region having an opening therein to serve as an alignment mark is provided. A dielectric layer is formed overlying the substrate and fills the opening, followed by the multi-layer hard mask. The multi-layer hard mask over the opening is partially removed and that on the device region is patterned to form a plurality of holes therein and expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form the plurality of contact holes therein.

REFERENCES:
patent: 6140226 (2000-10-01), Grill et al.
patent: 6479391 (2002-11-01), Morrow et al.
patent: 6514852 (2003-02-01), Usami
patent: 6774439 (2004-08-01), Fukuzumi et al.
patent: 2004/0175926 (2004-09-01), Wang et al.
patent: 2005/0042871 (2005-02-01), Tzou et al.
patent: 03138920 (1991-06-01), None
patent: 589708 (2004-06-01), None

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