Contact de-bouncing circuit with common mode rejection

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307216, 307247A, 340365E, H03K 518

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active

041852109

ABSTRACT:
A circuit for preventing the simultaneous application of contradictory input commands to a system and for filtering-out signals of shorter duration than a given period. The circuit includes an EXCLUSIVE-OR type gate adapted to receive input commands, whose output is "True" only when one of the input commands is present and no contradictory condition exists. The output of the gate is coupled to the input of a first flip flop which is set to a state indicative of the presence of the "True" signal at its input, when clocked at some time t.sub.1. The output of the first flip flop is logically combined with the one input command that is present to produce a signal which is applied to the input of a second flip flop. The second flip flop is placed in a state indicative of the value of its input, when clocked at some time t.sub.2, subsequent to t.sub.1. The one input command must be present for the duration t.sub.1 -t.sub.2 to place the second flip flop in its set state. Thus, two or more input signals of like binary significance applied at the same time are blocked and contact bounce or noise of shorter duration than the fixed period t.sub.1 -t.sub.2 is prevented from causing erroneous operation.

REFERENCES:
patent: 2946897 (1960-07-01), Mayo
patent: 2947945 (1960-08-01), Relis et al.
patent: 3721833 (1973-03-01), Kramer
patent: 3795823 (1974-03-01), Morgan et al.
patent: 3828258 (1974-08-01), Hills et al.
patent: 3979609 (1976-09-01), Schillhof
patent: 4028878 (1977-06-01), Droz et al.
patent: 4057738 (1977-11-01), Nishimura
J. H. Hubbard et al., Glitch Free Pulse Generation and Contact Closure Detection, IBM Technical Disclosure Bulletin, vol. 19, No. 3, Aug. 1976, pp. 816-817.
John M. Irwin, "Coincident Pulse Eliminator," The Electronic Engineer, Mar. 1970, p. 85.

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