Active solid-state devices (e.g. – transistors – solid-state diode – Folded bit line dram configuration
Reexamination Certificate
2000-08-07
2003-02-04
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Folded bit line dram configuration
C257S908000, C257S909000
Reexamination Certificate
active
06515374
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a contact connection of metal interconnects of an integrated semiconductor chip which are disposed orthogonally with respect to one another in different metallization planes.
The structure of an integrated semiconductor chip generally exhibits a plurality of metallization planes that are parallel to one another. The various metallization planes each contain metal interconnects for electrically connecting different circuit sections of the integrated circuit. The metal interconnects of two different metallization planes are connected to one another via contact points which establish an electrically conductive connection between the metal interconnects.
Layout structures of an integrated semiconductor chip are usually aligned in wide regions according to an orthogonal grid. Therefore, for example, the metal interconnects of different metallization planes run parallel or at a right angle to one another. The layout of an integrated semiconductor chip is in this case generally oriented to a right-angled coordinate system with which the various manufacturing processes in the course of fabricating a semiconductor module are usually coordinated. As a consequence thereof, structures which are aligned according to an orthogonal grid can generally be manufactured faster and more precisely. For example, structures that are diagonal relative thereto can only be approximated in a step-like manner, which may require a corresponding data density and, in individual cases, a longer fabrication time.
If two mutually orthogonal metal interconnects of two different metallization planes are contact-connected to one another, use is usually made, primarily for the reasons mentioned above, of contacts whose areas fit into the orthogonal grid. For example, if the contact area of a contact is wider than one of the metal interconnects or contact connection is to be effected via a plurality of contacts along the metal interconnects, then it is necessary that the metal interconnects that are to be contact-connected run parallel to one another in a section corresponding to the length of the contact point to be provided. To ensure that at the contact points the material nature of the metal interconnects is influenced as little as possible by electromigration, it is the case, moreover, that as far as possible no right-angled changes in the direction of the metal interconnects should be provided.
Customary concepts hitherto for contact connection provide mutually orthogonal metal interconnects which, for the purpose of contact connection, approximate to a parallel course in a step-like manner, for example, resulting in a relatively high space requirement on the chip area. Other concepts for contact connection provide contact connection at other more suitable locations, but this usually results in additional complexity in the layout configuration process.
SUMMARY OF THE INVENTION
The object of the present invention is to specify a semiconductor chip having at least two mutually orthogonal metal interconnects of two different metallization planes which are contact-connected to one another in such a way that the requisite space requirement is as small as possible and the influence of electromigration is reduced as much as possible.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated semiconductor chip. The semiconductor chip contains metal interconnects having a first region and a second region and, including, at least one first metal interconnect of a first metallization plane and a second metal interconnect of a second metallization plane running parallel to the first metallization plane. At least one electrically conductive contact point is disposed between the first and second metal interconnects. The first and second metal interconnects are disposed orthogonally with respect to one another in the first region and the first and second metal interconnects are not contact-connected to one another by the contact point in the first region. In the second region, the first and second metal interconnects are disposed parallel to one another and at an oblique angle to directions of the first and second metal interconnects in the first region. Finally, the first and second metal interconnects are contact-connected to one another by the contact point in the second region.
The integrated semiconductor chip has at least two metal interconnects of two different metallization planes, which are disposed parallel to one another. The metal interconnects are electrically connected to one another by the electrically conductive contact point. The metal interconnects, for each direction, run orthogonally with respect to one another in a first region, in which they are not contact-connected to one another via the contact point. The metal interconnects, for each direction, run parallel to one another and at an oblique angle to the directions of the metal interconnects of the first region in a second region, in which they are contact-connected to one another via the contact point. Therefore, on account of the oblique-angled configuration, right-angled changes in direction that promote the influence of electromigration are not necessary for the purpose of contact connection. A configuration of this type additionally obviates the need, mentioned in the introduction, for stepwise approximation, thereby enabling a space-saving configuration of the metal interconnects.
In order to keep the influence of the electromigration as uniformly low as possible for all the metal interconnects, it is advantageous to disposed the metal interconnects, for each direction, at an angle of 45° to the directions of the metal interconnects of the first region.
In a customary embodiment, the contact point has a rectangular area parallel to the metallization planes. If the intention is for the layout of the contact point not to be changed with regard to previous contact-connection concepts, then the area of the contact point is disposed edge parallel to the metal interconnects of the first region. This may, however, require the metal interconnects to be widened in the contact-connection region, since the edges of the contact area and the metal interconnects are disposed at an oblique angle to one another and the contact point thereby occupies a larger width on the metal interconnects.
In order not to influence the width of the metal interconnects it is advantageous to dispose the area of the contact point edge parallel to the metal interconnects of the second region. Therefore, a portion of the edges of the contact area and the edges of the metal interconnects run parallel to one another in the contact-connection region.
In order to improve the contact connection, it is favorable for the metal interconnects to be connected to one another in the contact-connection region via a plurality of contact points disposed along the metal interconnects. With the configuration of the contact point in accordance with the invention, the requisite space requirement is not significantly increased as a result.
The invention can generally be applied to all semiconductor chips which have contact connection of metal interconnects of two metallization planes. With the progress in data processing and data storage and with the further development of the technical processes required for fabrication, it is becoming increasingly possible for structures of an integrated circuit which are not matched to a predetermined orthogonal layout grid to be produced faster and with increasing precision.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a contact connection of metal interconnects of an integrated semiconductor chip, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and
Bänisch Andreas
Kling Sabine
Cao Phat X.
Greenberg Laurence A.
Infineon - Technologies AG
Le Thao X.
Locher Ralph E.
LandOfFree
Contact connection of metal interconnects of an integrated... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Contact connection of metal interconnects of an integrated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Contact connection of metal interconnects of an integrated... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3146161