Construction of scanning or imaging arrays suitable for...

Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices

Reexamination Certificate

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C257S686000, C257S723000, C361S760000, C361S803000

Reexamination Certificate

active

06252780

ABSTRACT:

FIELD OF THE INVENTION
The present invention is directed to very large linear arrays of either photosensors or image-creating structures, which can be made to relatively long lengths, such as up to 50 inches, such as to create or record posters or engineering drawings.
BACKGROUND OF THE INVENTION
Image sensors for scanning document images typically have a row or linear array of photosensors together with suitable supporting circuitry integrated onto a silicon chip. Analogous devices for creating images in response to digital image data, such as LED printbars in xerographic printers, or ink-jet printheads, include a linear array of image creating structures similarly integrated onto a silicon chip. In either case, because of the difficulty in economically designing and fabricating an array comparable in length to the width of an image to be created or recorded, various additional structures must be used. In the scanning context, it is typical to require optical reduction of an original image so the light from the image is reduced to the array of a single chip; in ink-jet printing, a single chip is caused to reciprocate for numerous swaths across an image substrate. However, it would be preferable in many ways to provide a structure, either for recording or image creation, which creates or records a very large image on a one-to-one basis.
In the scanning context, there currently is available on the market a “full-width-array” scanning device, such as shown for example, in U.S. Pat. No. 5,272,113, in which up to 20 individual silicon chips, each with a small linear array of imaging structures thereon, are butted end-to-end to form what is effectively a single page-width array of photosensors. As alluded to in the '113 patent, a practical problem incident to abutting a plurality of chips into a single full-width array involves spacing the chips relative to each other so that the long array of photosensors formed by the plurality of chips is of a substantially even spacing with a minimum of anomalies, particularly between the last photosensor of one chip and the first photosensor of the next. Further complicating the spacing problem is the question of the thermal coefficient of expansion, or TCE, of the chips themselves, and in particular of the chips relative to the member on which the chips are mounted within the apparatus. Such a thermal mismatch could cause undesirable bowing of the assembly, much in the manner of a bimetallic strip. Such mechanical stressing of the relatively brittle silicon chips is likely to damage the chips.
In the context of apparatus for recording or creating very large images such as posters or engineering drawings, which may be up to 50 inches long in a critical dimension, the creation of very long imaging structures out of butted silicon chips becomes highly problematic. The present invention is directed to a structure of a very long linear array of imaging chips (such as comprising photosensors, LEDs, or portions of ink-jet ejectors) in which some of the practical problems are surmounted.
DESCRIPTION OF THE PRIOR ART
U.S. Pat. No. 4,954,197 discloses a process for fabricating a full-width array in which a plurality of small chips are bonded onto the metallic covering of an elongated substrate by an electrically conductive heat activated adhesive, in which a photocurable adhesive is used to temporarily retain the smaller chips in position while the heat activated adhesive is cured.
U.S. Pat. No. 4,976,802 discloses a process for fabricating a long scanning or printing array, in which a number of chips are bonded onto a glass substrate using a photocurable adhesive to form a subassembly. The subassembly is then inverted and joined to a second substrate having a conductive surface using a conductive heat activated adhesive.
U.S. Pat. No. 5,034,083 discloses a process for fabricating a scanning or printing array, in which a number of small scanning or printing chips are bonded onto the surface of a glass substrate having an opaque thermally and/or electrically conductive coating thereon, with the coating removed at discrete sites to allow a photocurable adhesive placed at the sites to be cured through exposure to UV light from underneath the substrate.
U.S. Pat. No. 5,272,113 discloses a photosensor array in which semiconductor chips are mounted on a substrate. After the chips are tacked onto the substrate with uncured epoxy, the assembly is brought to a low temperature prior to the heating of the curing step. The cooling step enables the tacked chips to self-space before the epoxy is cured.
U.S. Pat. No. 5,528,272 discloses a full-width array structure having materials with both a high thermal coefficient of expansion and a low thermal coefficient of expansion. A suitable adhesive provides lateral give while firmly holding the respective components together. Since the various components expand and contract from a center location of the assembly, the center location is bonded by an adhesive which does not provide lateral give, so that alignment between parts are maintained while the remainder of the respective components float relative to each other and prevent thermally induced stresses.
SUMMARY OF THE INVENTION
According to the present invention, there is provided an imaging apparatus, comprising a first printed wiring board and a second printed wiring board, arranged whereby an edge of the first printed wiring board is adjacent an edge of the second printed wiring board, creating a seam therebetween. The first printed wiring board and the second printed wiring board each define a first main surface and a second main surface. A set of semiconductor chips are attached to the first main surface of each of the first wiring board and second wiring board. At least a portion of the second main surface of each of the first wiring board and second wiring board are attached to a second-layer board, whereby the seam between the first printed wiring board and the second printed wiring board is spaced from an edge of the second-layer board.


REFERENCES:
patent: 4954197 (1990-09-01), Jedlicka et al.
patent: 4976802 (1990-12-01), LeBlanc
patent: 5034083 (1991-07-01), Campanelli et al.
patent: 5272113 (1993-12-01), Quinn
patent: 5329418 (1994-07-01), Tanabe
patent: 5426566 (1995-06-01), Beilstein
patent: 5428190 (1995-06-01), Stopperan
patent: 5521794 (1996-05-01), Hargrave et al.
patent: 5528272 (1996-06-01), Quinn et al.
patent: 5691209 (1997-11-01), Liberkowski
patent: 6121988 (2000-09-01), Uchiyama

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