Constraint driven insertion of scan logic for implementing desig

Details Constraint driven insertion of scan logic for implementing desig Constraint driven insertion of scan logic for implementing desig

1995-12-29

1999-05-11

Voeltz, Emanuel Todd

Boots, shoes, and leggings

364489, 364490, G06F17/50;17/00

Patent

active

059034661

ABSTRACT:
A computer implemented process and system for providing a scan insertion process having a reduced set of constraint driven compiler optimizations that provide an efficient and effective optimization for design for test implementations. The present invention includes a three tiered effort performance optimization process within a scan insertion process; a first tier operates to perform a set of optimizations (size design) only on elements of the design added for design for test (DFT). The second tier offers the first tier and performs the size design optimizations across all of the design while the third tier offers the second tier with sequential optimizations, circuit size downs, and another size design. Each higher user-selectable tier offers more complex optimizations and consumes additional processing time. An option to perform design constraints optimization (max fanout, max signal transition, and max capacitance) is also available. By utilizing a reduced set of performance optimizations, the present invention offers a post scan insertion compile technique that is fast enough to be practically used on chip level netlists. Hierarchical compilations for DFT are therefore allowed. Since the modified scan insertion procedure can operate in conjunction with a TR compiler of the present invention, the modified scan insertion procedure breaks loopback connections and generates proper scan chains. The scan insertion process of the present invention is compatible with netlists that contain a mixture of scan cells and non-scan cells.

REFERENCES:
patent: 5522063 (1996-05-01), Ashar et al.
patent: 5572436 (1996-11-01), Dangelo et al.
patent: 5592493 (1997-01-01), Crouch et al.
patent: 5696771 (1997-12-01), Beausang et al.
patent: 5703789 (1997-12-01), Beausang et al.
Bolchini et al. "A Wafer Level Testability Approach Based On an Improved Scan Insertion Technique," IEEE, pp. 438-447, Aug. 1995.
Bolchini et al. "Towards WSI Testable Devices: An Improved Scan Insertion Technique," IEEE, pp. 339-348, Jan. 1995.
Riessen et al. "Designing And Implementing an Architecture With Boundary Scan," IEEE, pp. 9-19, Feb. 1990.

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