Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2002-09-11
2004-05-11
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S543000, C323S315000
Reexamination Certificate
active
06734719
ABSTRACT:
CROSS-REFERENCE TO PRIOR APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-278460, filed on Sep. 13, 2001, the entire content of which is incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates generally to voltage generating circuitry adaptable for use in semiconductor integrated circuit devices and, more particularly, to a constant voltage generation circuit capable of generating a high output voltage even upon occurrence of a potential decrease in power supply voltage.
DESCRIPTION OF THE RELATED ART
FIG. 9A
is a diagram showing one typical prior known constant voltage generation circuit. This constant voltage generation circuit
1
is equipped with a constant current generator circuit
10
of the so-called Wilson type which functions to output a constant-level voltage and a switching circuit
20
operable to switch between its active state and inactive state.
The Wilson type constant current generator circuit
10
is generally configured from a p-channel metal oxide semiconductor (pMOS) transistor p
1
of the enhancement type (E-type) which has a standard threshold voltage (Vtp) with a negative value, an E-type pMOS transistor p
2
which is the same in size as the transistor p
1
, an E-type n-channel MOS (nMOS) transistor n
1
having a low threshold voltage Vtn1, and an E-type nMOS transistor n
2
having its threshold voltage Vtn2 higher than this Vtn1 value.
The transistor p
1
is diode-connected—that is, its drain and gate are connected together. The language “diode-connected” will be used hereinafter in the same technical meaning. The transistors p
1
and p
2
have gates coupled together, thereby making up a current mirror circuit. The nMOS transistor n
1
and a resistor
11
are connected between the drain of this transistor p
1
and ground voltage Vss, thus forming a first current flow path
12
. This resistor
11
has a resistance value R1, which is larger than the turn-on resistance of the nMOS transistor n
1
.
The nMOS transistor n
2
and a switching transistor
24
of a switching circuit
20
as will be later described are connected between the drain of transistor p
2
and ground voltage Vss to thereby form a second current flow path
13
. The transistor n
1
's gate is connected to the gate and drain of the transistor n
2
. A potential NBIAS at the drain of this transistor n
2
is for use as an output voltage Vo of the constant voltage generation circuit
1
.
The switching circuit
20
is constituted from a switching pMOS transistor
21
, a switching nMOS transistor
22
, an inverter
23
, and a switching nMOS transistor
24
. The pMOS transistor
21
is connected between the source of pMOS transistor p
1
and a power supply voltage Vcc. In responding to receipt of an enable signal ENB such as shown in
FIG. 9B
, the transistor
21
performs a switching operation to go from its turn-on state to turn-off state, whereby the first current flow path
12
made up of the pMOS transistor p
1
and nMOS transistor n
1
turns on. Note here that although a pMOS transistor
25
which has the same characteristics as the switching pMOS transistor
21
is connected on the pMOS transistor p
2
side also, this is merely for the purpose of equalizing potential levels at the sources of the both transistors p
1
, p
2
. Transistor
25
is coupled to ground at its gate. Thus, transistor
25
is always kept conductive—i.e. turns on in any events.
The nMOS transistor
24
is disposed between the source of nMOS transistor n
2
and ground voltage Vss and is designed to switch from its turn-off to turn-on state in response to receipt of the enable signal ENB. Whereby, the second current flow path
13
made up of the pMOS transistor p
2
and nMOS transistor n
2
turns on. The switching nMOS transistor
22
is the one that is operatively responsive to receipt of the enable signal ENB for performing reset and set-up of a connection node O
1
.
An operation of the circuitry of
FIG. 9A
is as follows. Upon receiving of the enable signal ENB, the switching circuit
20
causes the Wilson constant current generator circuit
10
to switch from its inactive state to active state. Due to the current mirror connection of the transistors p
1
, p
2
, a current Ip
2
which flows between the source and drain of pMOS transistor p
2
becomes equal to a current Ip
1
flowing between the source and drain of pMOS transistor p
1
. These currents Ip
1
, Ip
2
flow into the nMOS transistors n
1
, n
2
, respectively, thereby becoming currents In
1
, In
2
. Thus, In
1
and In
2
also are equal to each other. As the resistance value R1 of resistor
11
is made larger than the turn-on resistance of nMOS transistor n
1
, the current versus voltage characteristics of the current flow path
12
is representable by straight line “A” (with a gradient of 1/R1) shown in a graph of
FIG. 9C
, wherein line A crosses the lateral axis of this graph at a value Vtn1. On the other hand, the current-voltage characteristics of the current flow path
13
may be represented by exponential curve “B” with intercept Vtn2 on the lateral axis. The output voltage Vo of the constant voltage generation circuit
1
is determinable by a cross point C (operating point) of the characteristic line A and curve B owing to the functionality of the current mirror connection of transistors p
1
, p
2
; thus, it becomes a constant voltage without any potential dependency on the power supply voltage Vcc—say, Vcc-independent constant voltage. Additionally, curve D is plotted in
FIG. 9C
to indicate the transistor p
1
's load curve whereas curve E indicates a drain current Ip
2
of the transistor p
2
and its load curve.
Unfortunately the constant voltage generation circuit shown in
FIG. 9
is encountered with a problem which follows. In cases where the supply voltage Vcc potentially decreases or drops down in accordance with the scaling of on-chip circuit elements, it is difficult to guarantee provision of the output voltage required. More specifically, in the constant voltage generation circuit of
FIG. 9
, the minimum value Vccmin of the supply voltage Vcc for operation stability is determined by the first current flow path
12
and is given as follows:
Vccmin=Vo−Vtn
1+|
Vtp|+dVds
1, [Formula 1]
where dvds
1
is the drain-source voltage of transistor p
1
.
As can be seen from Formula 1, the only approach to reducing Vccmin while maintaining the output voltage Vo at the required potential level is to lower the threshold voltage Vtp.
This approach, however, does not come without accompanying a problem as to an increase in production costs due to the necessity for “special” channel implantation processes. Consequently, the prior art circuitry suffers from a problem that Vccmin reduction is hardly achievable without lowering the output voltage Vo per se.
SUMMARY OF THE INVENTION
The present invention may provide a constant voltage generating circuit in accordance with a first aspect thereof, which comprises a first constant current generation circuit which includes a first transistor and a second transistor and generates a first voltage and a first current as determined depending on a difference in threshold voltage between the first and second transistors, a second constant current generation circuit configured to generate a second current that is proportional to the first current, and a voltage generation circuit which includes a third transistor having its gate and drain connected together and which generates a second voltage when the second current flows in the third transistor.
The present invention may provide a constant voltage generating circuit in accordance with a second aspect thereof, which comprises a first constant current generation circuit which includes a first transistor and a second transistor and generates a first voltage and a first current as determined depending on a difference in transconduntance between the first and second transistors, a second constant c
Takano Yoshinori
Tanzawa Toru
Cunningham Terry D.
Kabushiki Kaisha Toshiba
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