Constant voltage generating circuit

Details Constant voltage generating circuit Constant voltage generating circuit

1999-10-12

2001-09-04

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S542000, C327S513000, C323S314000

Reexamination Certificate

active

06285245

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to a constant voltage generating circuit (reference voltage power supply circuit). In particular, the present invention pertains to a constant voltage generating circuit (reference voltage power supply circuit) for an electronic circuit which has a low temperature dependence and can be operated at a low power supply voltage.
BACKGROUND OF THE INVENTION
FIG. 1
is a circuit diagram illustrating an ECL (Emitter Coupled Logic) inverter/buffer circuit as an example of the electronic circuit to which the constant voltage generating circuit of the present invention can be applied.
The ECL inverter/buffer circuit has second and third npn bipolar transistors Q
2
and Q
3
whose emitters are connected together and which can function as a differential amplifier. The ECL inverter/buffer circuit also has load resistors RL, RL of the same resistance value arranged between the collectors of transistors Q
2
, Q
3
and the supply part (supply rail) of the first power supply voltage V
cc
. In addition, the ECL inverter/buffer circuit has a first npn bipolar transistor Q
1
used as a constant current source and a first resistor RE
1
which are connected between the supply rail of the second power supply voltage V
EE
and the connection node of the emitters of transistors Q
2
and Q
3
.
The ECL inverter/buffer circuit has a fourth npn bipolar transistor Q
4
, which acts as an output buffer, and whose collector is connected to the supply rail of the first power supply voltage V
CC
. The first output signal at the collector of the second transistor Q
2
is applied to the base of the fourth bipolar transistor. A sixth npn bipolar transistor Q
6
, which acts as a constant current source for transistor Q
4
, and a second resistor RE
2
are connected between the emitter of transistor Q
4
used as the output buffer and the supply rail of the second power supply voltage V
EE
.
The ECL inverter/buffer circuit also has a fifth npn bipolar transistor Q
5
, which acts as an output buffer, and is connected to the supply rail of the first power supply voltage V
CC
. The second output signal at the collector of the third transistor Q
3
is applied to the base of the fifth bipolar transistor. A seventh npn bipolar transistor Q
7
, which acts as the constant current source of transistor Q
5
, and a third resistor RE
3
are connected between the emitter of transistor Q
5
used as the output buffer and the supply rail of the second power supply voltage V
EE
.
In the ECL inverter/buffer circuit shown in
FIG. 1
, a signal corresponding to the difference between the first input signal AY applied to the base of the second transistor Q
2
and the second input signal AX applied to the base of the third transistor Q
3
is output to the collectors of the second and third transistors Q
2
and Q
3
. The output signals are applied to the bases of the fourth and fifth transistors Q
4
and Q
5
which are used as the output buffers. The final output signals X and Y are output from the emitters of said transistors Q
4
and Q
5
, respectively.
In the ECL inverter/buffer circuits shown in
FIG. 1
, a control voltage (or reference voltage) V
CS
is applied to the bases of transistors Q
1
, Q
6
, and Q
7
used as the constant current sources such that control currents I
CS
of equal value flow from said transistors Q
1
, Q
6
, and Q
7
through resistors RE
1
-RE
3
, respectively.
In the ECL inverter/buffer circuits shown in
FIG. 1
, the first to the third resistors RE
1
-RE
3
have the same resistance of R
e
.
The amount of current I
CS
flowing through transistors Q
1
, Q
6
, and Q
7
is relatively large.
In the ECL inverter/buffer circuit shown in
FIG. 1
, there are three constant current sources. Consequently, the power consumption is V
CC
×I
CS
×3 (V
CC
is the value of the power supply voltage V
CC
, and I
CS
is the value of the control current I
CS
).
The control current I
CS
flowing through transistors Q
1
, Q
6
, and Q
7
is defined by the following formula 1.
I
CS
=(V
CS
−V
BE
)/R
e
  (1)
where V
CS
is the reference voltage (control voltage) applied to the bases of transistors Q
1
, Q
6
, and Q
7
;
V
BE
is the base-emitter voltage (pn junction voltage) of transistors Q
1
, Q
6
, and Q
7
; and R
e
is the resistance of the first to third resistors RE
1
-RE
3
.
When the total power consumption of a logic integrated circuit (logic IC) formed by integrating many logic circuits including the ECL inverter/buffer circuit shown in the FIG. is calculated on the bases of the aforementioned current consumption, it is found that the power consumption of the entire IC chip is in the range of one to several watts. The surface temperature of the IC chip becomes high due to the heating caused by the current consumed.
In addition to finding an effective heat dissipation method to prevent the aforementioned heating problem, it is also necessary to find a means which can effectively prevent “thermal runaway,” which will destroy the IC chip as a result of repeating the cycle in which the chip is heated by the current consumed, and which in turn further increases the current consumption.
In order to prevent thermal runaway, the temperature coefficient of control current I
CS
is preferrably to be negative. In formula 1, the temperature coefficient of the pn junction voltage V
BE
of the bipolar transistor is negative. It is usually −2 mV/° C. Consequently, the temperature coefficient of control voltage V
CS
must be greater than −2 mV/° C. It is also necessary to control the temperature coefficient of control voltage V
CS
in consideration of the temperature coefficients of resistors RE
1
-RE
3
. If the temperature coefficients of the resistors are negative, by adding these temperature coefficients, the temperature coefficient of control voltage V
CS
must have an even larger negative value. Also, it is preferred that [the temperature coefficient of the control voltage] be constant irrespective of the changes in the first and second power supply voltages V
CC
and V
EE
.
Based on the aforementioned point of view, a conventional constant voltage generating circuit (reference voltage generating circuit) used for generating the control voltage (reference voltage) applied to the bases of transistors Q
1
, Q
6
, and Q
7
in the ECL inverter/buffer circuit shown in
FIG. 1
or a voltage applied to another electronic circuit will be explained with reference to
FIGS. 2 and 3
.
The constant voltage generating circuit (reference voltage generating circuit) shown in
FIG. 2
is a well-known constant voltage generating circuit called a bandgap reference circuit.
The bandgap reference-type constant voltage generating circuit has a reference current source circuit I
ref
, an npn bipolar transistor Q
11
, an npn bipolar transistor Q
12
whose base is connected to its collector and can function as a pn junction diode, as well as resistors RC
1
, RC
2
, and RE. The constant voltage generating circuit also has a buffer circuit BUF, which is an amplifier circuit with a gain of 1 and has an npn bipolar transistor Q
13
(not shown in the FIG.) incorporated.
As can be seen from the FIG., a current-mirror constant-current source is formed by transistors Q
11
and Q
12
.
In the constant voltage generating circuit shown in
FIG. 2
, a voltage V
CS
of prescribed value can be output from buffer circuit BUF by setting the values of resistors RC
1
, RC
2
, and RE appropriately.
In the constant voltage generating circuit shown in
FIG. 2
, it is believed that transistors Q
1
and Q
12
used for forming the current mirror type current source circuit have the same characteristics. Consequently, the voltage V
RE
across resistor RE can be expressed by the following formula.
V
RE
=V
BE
(Q
12
)−V
BE
(Q
11
)=(kT/q)×1n(I
c2
/I
c1
)  (2)
where, V
BE
(Q
11
) is the base-emitter voltage of transistor Q
11
,
V
BE
(Q
12
) is the base-emitter voltage of transistor Q
12
,
I
c1
is the current flowing through resistor RC
1
,
I
c2
is

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