Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1999-03-31
2001-11-27
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
Reexamination Certificate
active
06323725
ABSTRACT:
BACKGROUND OF THE INVENTION
I. Field of the Invention The invention generally relates to integrated circuits and in particular to constant transconductance CMOS bias circuits for biasing NMOS differential pairs such as those employed in differential amplifiers.
II. Description of the Related Art NMOS differential pairs ac commonly employed within integrated circuits as high-speed components of differential amplifiers, sample and hold circuits, and the like. Constant transconductance bias circuits are employed in connection with the NMOS differential pairs for reducing or eliminating temperature and process variations of the gm of the differential pair. By way of example, the operation of a constant transconductance bias circuit is described in the following in connection with a differential pair containing an NMOS differential pair.
FIG. 1
illustrates a simple NMOS differential pair
10
. The pair of NMOS devices
12
and
14
have rates connected to a pair of voltage input lines
16
and
18
, respectively. A transconductance (g
m
) of the differential pair is &Dgr;i/&Dgr;V
in
where &Dgr;V
in
is the input voltage differential and &Dgr;i is the current through one of the devices of the differential pair. To prevent temperature and process variations from affecting the gm of the differential pair, the pair is biased by a bias voltage applied to the gate of an NMOS device
24
connected between the sources of devices
16
and
18
and ground. The bias voltage is generated by a bias circuit
26
which operates to generate a constant transconductance (g
m
) bias signal despite temperature and process variations. Briefly, the bias circuitry includes a pair of NMOS devices
28
and
30
connected between a pair of nodes A and B and ground, respectively. A pair of PMOS devices
32
and
34
arc connected, respectively, between nodes A and B and the positive voltage source. Gates of NMOS devices
28
and
30
are connected to node A. Gates of NMOS devices
32
and
34
are connected to B. A transconductance-setting resistor
36
is connected between the source of device
30
and ground. Resistor
36
is typically located off-chip to permit the resistance to be set after chip fabrication for better tolerance.
In use, bias circuitry
26
operates to generate a bias current that sets the transconductances of NMOS devices
12
and
14
of the differential pair to an amount inversely proportional to the resistance of transconductance-setting resistor
36
. The bias circuit is, in effect, a modification of a MOS self-biasing Widlar current source, well known in the art. The constant transconductance of the NMOS devices of the differential pair may be established using the following equations (with the various terms in the equations having their standard definitions in the art):
vgs1=vgs2+IR
vgs2=vgs1+I·R
Since
vgs
=
2
·
I
B
-
Vt
B=&mgr;nCoxW/L
and
2
·
I
B
=
1
2
·
2
·
I
B
+
I
·
R
then
Solving for
I
=
1
2
·
B
·
R
yields
gm
=
2
·
B
·
I
=
1
R
Thus, disregarding body effects the transconductances of the devices of the differential pair are merely inversely proportional to the resistance of the transconductance-setting resistor. Unfortunately, in practical integrated circuits, body effects can pose a significant problem. Briefly, body effects relate to a modification of the threshold voltage Vt caused by a voltage difference between source and substrate. The change in voltage threshold is proportional to the square root of the voltage between the source and the substrate. Differences in voltage between the source and the substrate occurs as a result of voltage drop across transconductance-setting resistor.
In the circuit of
FIG. 1
, the change in threshold voltage results in two separate problems. The first problem occurs from the variations in source voltage between NMOS devices
28
and
30
of the bias circuitry. Since the source of NMOS device
30
is at a different voltage from that of device
28
, the transconductance is not merely proportional to the resistance of resistor
36
but is instead given by the following equation:
g
m
=
1
+
1
+
2
·
B
·
R
·
vterr
2
R
B
=
μ
n
Cox
W
L
.
where
This formula for transconductance may be derived from the following set of equations:
vgs1=vgs2+IR−vterr
vgs
=
2
·
I
B
-
vt
0
and since
B
=
μ
n
Cox
W
L
.
Then
2
·
I
B
=
1
2
2
·
I
R
+
I
·
R
-
vterr
.
Solving for
I
=
1
2
·
B
+
2
B
+
R
·
vterr
2
R
yields
g
m
={square root over (2+L ·B·I)}
and finally
g
m
=
1
+
1
+
2
·
B
·
R
·
vterr
2
R
.
The second body effect problem occurs as a result of absolute differences between the sources of devices
28
and
30
of the bias circuitry and devices
12
and
14
of the differential pair. The absolute current generated in the bias cell is proportional to the threshold voltage, and therefore any variances between the source voltages will result in a different transconductance value. Since the input common mode voltage to the differential pair is fixed, the source voltage of devices
12
and
14
will vary with process causing a non-tracking transconductance. As a result, temperature and process variations are not fully compensated for by the CMOS bias circuitry of
FIG. 1
resulting in uncertainties in the accuracy of the output of the differential pair.
As can be appreciated, it would be highly desirable to provide an improved constant transconductance bias circuit for use with an NMOS differential pair that substantially eliminates variations caused by body effects and it is to that end that aspects of the invention are primarily directed.
SUMMARY OF THE INVENTION
In accordance with a first aspect of the invention, a bias cell for use in biasing a differential pair, such as an NMOS differential pair, is provided wherein a voltage threshold mismatch between NMOS devices of the bias cell is substantially eliminated to thereby reduce variations in transconductance caused by body effects. The bias cell includes a pair of current source devices with a transconductance-setting resistor connected between gates of the pair of current source devices. The current through the resistor generates a voltage needed to operate the gm bias cell. A bias line connects the voltage-setting circuitry to the differential pair.
By positioning the transconductance-setting resistor between the gates of the NMOS devices of the bias cell, rather than between the source of one of the device and ground, a voltage differential between the sources is eliminated thereby removing any threshold voltage mismatch. Hence, body effect variations that might affect the voltage threshold do not cause a significant change in the transconductance of the bias cell and hence do not cause a significant change in the output bias current.
In accordance with a second aspect of the invention, a bias cell for use in biasing an NMOS differential pair is provided wherein a source voltage mismatch between sources of the NMOS devices of the bias cell and sources of NMOS devices of the differential pair is substantially eliminated to thereby also reduce variations in transconductance caused by body effects. The bias cell includes a pair of current source devices with source follower circuitry connected to sources of the pair of current source devices. The source follower circuitry has a gate voltage set to input a common mode voltage of the differential pair. A bias line connects the source follower circuitry to the differential pair.
By providing the source follower circuitry with gate voltage set to input the common mode voltage, any absolute differences between the sources of the NMOS devices of the bias cell and the sources of the differential pair is eliminated thereby further reducing variations in transconductance caused by body effects.
In some embodiments, the bias cell includes both the transcon
Bazarjani Seyfollah
Goldblatt Jeremy Mark
Brown Charles D.
Edmonston Brian S.
Qualcomm Incorporated
Wadworth Philip R.
Zweizig Jeffrey
LandOfFree
Constant transconductance bias circuit having body effect... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Constant transconductance bias circuit having body effect..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Constant transconductance bias circuit having body effect... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2569559