Constant duty-cycle limiting of analog input signal swing in...

Details Constant duty-cycle limiting of analog input signal swing in... Constant duty-cycle limiting of analog input signal swing in...

2000-04-25

2001-11-20

Mottola, Steven J. (Department: 2817)

Amplifiers

Miscellaneous

Amplifier protection means

C330S251000

Reexamination Certificate

active

06320465

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to class-D amplifiers, and, in particular, to integrated Pulse Width Modulation (PWM) audio amplifiers.
BACKGROUND OF THE INVENTION
The demands for reducing power dissipation and optimizing efficiency has recently favored the development and utilization of Pulse Width Modulation (PWM) or Pulse Density Modulation (PDM) class-D amplifiers. This has even been the case for typical analog applications, such as audio and electro-acoustic amplifiers, for example.
According to a common approach, the analog signal is converted into a constant frequency digital signal whose duty-cycle depends on the instantaneous value of the analog input signal. This produces a PWM, or alternatively, a PDM signal whose average value is an amplified signal that is substantially a replica of the analog input signal.
This is normally done by a converter that converts an analog input signal into a digital signal, for example, a PWM or a PDM signal. The converting is done by switching between the positive and negative supply voltages of the circuit. An average value of the digital signal represents an amplified replica of the analog input signal. The reconstruction of the analog signal takes place in an output low pass filter.
A functional scheme of such an amplifier is shown in FIG.
1
. The waveform of the output signal Vop is a square wave whose amplitude is equal to the supply voltage. A duty-cycle of the output signal Vop, according to the diagram of
FIG. 1
, is given by
D=T
1
/
Tsw=
(
Tsw−T
2
)/
Tsw
which depends on the Vin input signal. The diagram of
FIG. 1
represents the case in which the output signal is positive. Therefore, the duty-cycle is greater than 50%.
The average voltage Vo of the reconstructed signal on the load may be calculated as:
Vo
=(2*
D−
1)*
VDD
  (1)
The average value Vo is obtained from the output voltage Vop of the amplifying stage G by the low pass filter LC. The gain G of the amplifier is given by:
G=Vo/V
in  (2)
Equation (1) shows that for reproducing a positive output voltage Vo that approximates the positive supply value VDD, it is necessary a duty-cycle D approximates 1, and, therefore, a time T
2
is close to 0. However, an excessively small interval T
2
may cause at least two problems in a class-D amplifier.
A first problem arises because the output switching of the amplifying stage have a finite rate. If &Dgr;T is the switching time and T
2
becomes less than 2&Dgr;T, the output waveform is strongly distorted as illustrated in
FIG. 2. A
B-type switching causes a strong output distortion, and, therefore, a distortion of the audio signal.
A second problem is that with the amplifiers that use a final stage with a bootstrap capacitance, the functioning is correct until the discharge of the capacitance is balanced by the charge of the bootstrap capacitance. Discharge of the capacitance occurs during the time Ti when the output is given by +VDD. The charge of the bootstrap capacitance occurs during the time T
2
when the output is low, i.e., at −VDD. If T
2
is close to 0, the bootstrap capacitance does not recharge, and, therefore, the functioning of the final stage may be compromised. Reference is directed to U.S. Pat. No. 5,818,209.
To address these problems, it is a common practice to limit the analog input signal Vin between two limiting thresholds. These two limiting thresholds are commonly dependent upon the actual voltages of the respective supply nodes VDD and −VDD.
FIG. 3
shows a complete scheme of a circuit LIMITER that limits the deviations of the analog output voltage VL within a pre-established voltage fraction &agr;<1 of the voltages of the two supply rails. The output signal VL of the circuit LIMITER, relative to an input sinusoid, is shown in FIG.
4
.
With respect to the maximum output voltage of the limiting stage, VLmax=&agr;VDD in terms of modulus, it is possible to establish through equation (1) the maximum duty-cycle Dlimit required by the final stage of the amplifier G. The amplifier is typically formed by a half-bridge stage that includes two power devices, a high-side device switching the output to the positive supply VDD node, and a low-side device switching the output to the negative supply node −VDD.
If G is the amplifier gain, the average voltage of the reconstructed output signal Vo is given by:
 
Vo=G*&agr;*VDD
  (3)
thus, from equation (1)
G*&agr;*VDD
=(2*
D
limit−1)*
VDD
  (4)
and by simplifying:
D
limit=(1+
G*&agr;
)*0.5  (5)
It would appear that by properly selecting the parameters from equation (5), the limit duty-cycle (Dlimit) could be determined.
In reality, equation (5) considers in a first approximation the series resistance of the amplifier's final stage as a null. In contrast, the delivery of current to the load occurs with a voltage drop on the series resistance of the low-side and high-side power devices. When the amplifier is delivering a positive current Io, the duty-cycle is greater than 50% and the output voltage Vop of the amplifying stage G has a characteristic as shown in FIG.
5
.
Indeed, VDD′ is smaller than VDD by an amount equal to the voltage drop on the series resistance of the high-side power device of the output half-bridge. If Ron is the series resistance of the high-side power device of the final stage and Io is the average output current at a given load of the amplifier, the VDD′ voltage is given by:
VDD′=VDD−R
on*
Io
  (6)
Similar considerations may also be made for a negative output current. The VDD″ voltage is equal to the −VDD minus the voltage drop on the low-side device of the final stage. By considering equation (6), it is evident that the apparent supply voltage of the final stage should not be considered fixed to VDD and −VDD, but varying with the output current Io and given by VDD′ and −VDD″.
The equation (1) used to determine the average output positive voltage becomes:
Vo=
(2*
D
−1)*
VDD′
  (7)
As a function of this new relation, the limit duty-cycle (Dlimit) may be recalculated corresponding to the maximum output voltage of the input limiting stage using equation (7) instead of equation (1).
With the same steps of equations (3), (4), and (5), the following equation is obtained:
D
limit=[1+
G*&agr;
*(
VDD/VDD
′)]*0.5  (8)
Since VDD′ is smaller than VDD, the real limit duty-cycle considered by equation (8) is greater than the one considered by equation (5). Moreover, the VDD′ depends on the output current and on the series resistance of the high-side power device of the output stage. This in turn depends on technical and manufacturing parameters, temperature, etc.
Similar considerations may be made also for a negative output voltage −VDD″, which is similarly limited by the voltage drop on the low-side power device of the output stage. Therefore, it is difficult to forecast with a sufficient precision the limit duty-cycle for any operating condition of the amplifier, and it is difficult to assure an optimal functioning of the final stage under all conditions.
SUMMARY OF THE INVENTION
In view of these difficulties, it is an object of the present invention to establish a constant limit duty-cycle substantially independent from fabrication process spreads, temperature, etc., and to assure an optimal functioning of the final stage of the amplifier for all working conditions.
A method of the invention comprises detecting the equivalent values VDD′ and −VDD″ of the voltages to which the output signal of the amplifier switches (or pseudo supplies). The method further includes making the limiting stage so that the voltage swing of an analog input signal utilizes the pseudo supply values VDD′ and −VDD″ as respective reference values to limit the voltage swings of the analog signal VL outpu

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