Constant delay logic circuits and methods

Details Constant delay logic circuits and methods Constant delay logic circuits and methods

1994-09-13

1997-02-04

Nelms, David C.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327285, 327291, 327295, H03H 1126, G06F 104

Patent

active

056002734

ABSTRACT:
A partitioned constant delay logic network 208 has a number of constant delay logic elements. The delay of each logic element is held constant by applying a controlled bias voltage, V.sub.bias. The source of the controlled bias voltage is a phase locked loop 201 which has a voltage controlled oscillator 203 constructed out of an odd plurality of constant delay logic elements.

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F. Gardner, "Phase Lock Techniques", 2nd Ed., John E. Wiley & Sons, pp. 8-16 & 121-125, 1966, New York.

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