Amplifiers – With semiconductor amplifying device – Including current mirror amplifier
Reexamination Certificate
2000-05-01
2002-09-17
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including current mirror amplifier
C330S257000, C323S315000
Reexamination Certificate
active
06452453
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a constant-current generator and a differential amplifier which depend little upon a power source voltage, and a semiconductor integrated circuit which includes the differential amplifier.
2. Description of the Related Art
Semiconductor integrated circuits, such as microcomputers and DRAMs, have had their operating speeds heightened year by year. There has been developed, for example, an SDRAM (Synchronous DRAM) in which an input/output interfacing circuit is operated at high speed in synchronization with a clock signal, thereby to write/read data at high speed.
FIG. 1
shows an input buffer which is used in the semiconductor integrated circuit of this kind.
The input buffer
1
is constructed of a constant-current generator
2
including a bias part
2
a
and a driver part
2
b
, and a differential amplifier
3
.
The bias part
2
a
is formed of a pMOS transistor
4
, and a resistor
5
having a high resistance. The pMOS transistor
4
has its source connected to a power supply line VDD, and has its drain and gate connected to a node N
1
. The resistor
5
has its one end connected to the node N
1
, and has its other end connected to a ground line VSS. The driver part
2
b
is formed of a PMOS transistor
6
. The pMOS transistor
6
has its source connected to the power supply line VDD, has its gate connected to the node N
1
, and has its drain connected to a node N
2
being the common source of the differential amplifier
3
. The PMOS transistors
4
,
6
are formed having equal sizes at proximate positions, and the threshold voltages VT
1
thereof are equalized. The constant-current generator
2
is constructed as a current mirror circuit.
The differential amplifier
3
includes a PMOS transistor
7
a
and an nMOS transistor
7
b
which are connected in series, and a PMOS transistor
8
a
and an nMOS transistor
8
b
which are also connected in series. Herein, a current mirror circuit is constructed of the transistors
7
b
,
8
b
. More specifically, the PMOS transistor
7
a
has its source connected to the node N
2
and its drain connected to the drain and gate of the nMOS transistor
7
b
, and it receives an input signal VIN
1
at its gate. The pMOS transistor
8
a
has its source connected to the node N
2
and its drain connected to the drain of the nMOS transistor
8
b
, and it receives an input signal VIN
2
at its gate. An output signal OUT is outputted from the common drain of the PMOS transistor
8
a
and the nMOS transistor
8
b
. The sources of the nMOS transistors
7
b
,
8
b
are connected to the ground line VSS.
Hereinbelow, the PMOS transistor and nMOS transistor shall be simply termed the “pMOS” and “nMOS”, respectively. In addition, the symbols VDD and VSS shall also denote a power supply voltage and a ground voltage, respectively.
FIG. 2
shows another input buffer
9
.
The input buffer
9
is configured of a constant-current circuit
10
in which a current mirror circuit is constructed of nMOSs (nMOS transistors), and a differential amplifier
11
in which a current mirror circuit is constructed of pMOSs (PMOS transistors). The input buffer
9
is such a circuit that the pMOSs and nMOSs of the input buffer
1
are replaced with each other, and that the power supply voltage VDD and the ground voltage VSS are replaced with each other.
Next, the operation of the input buffer
1
will be explained. Complementary clock signals supplied from the exterior, for example, are applied as the input signals VIN
1
, VIN
2
to the input buffer
1
shown in FIG.
1
.
The bias part
2
a
of the constant-current generator
2
generates a predetermined voltage V
1
at the node N
1
by the action of the pMOS
4
and the resistor
5
. Here, the resistance of the resistor
5
is set so that the voltage V
1
may become a value “(Power supply voltage VDD)−(Threshold voltage |VT
1
|)−-(Margin &agr;)”. Thus, the pMOSs
4
,
6
are reliably turned on owing to the margin &agr;.
A constant supply current IC is fed to the differential amplifier
3
by the turn-on operation of the PMOS
6
. Here, the differential amplifier
3
is designed so that the voltage V
2
of the node N
2
may become smaller than a value “(Power supply voltage VDD)−(Voltage V
1
)+(Threshold voltage |VT
1
|)”. Therefore, the pMOS
6
operates in the saturation region of static characteristics as shown in FIG.
3
. Accordingly, the supply current IC hardly changes even when the voltage V
2
of the node N
2
has changed to some extent under the influence of the operation of the differential amplifier
3
.
As shown in
FIG. 4
, the differential amplifier
3
receives the input signals VIN
1
, VIN
2
and outputs a differentially amplified signal as the output signal OUT.
Also in the input buffer
9
shown in
FIG. 2
, an operation similar to that of the input buffer
1
proceeds to differentially amplify input signals VIN
1
, VIN
2
and to produce an output signal OUT.
Meanwhile, SDRAMs have recently become higher in the frequency of a clock signal. Further, with a DDR-SDRAM (Double Data Rate-Synchronous DRAM), data signals are inputted/outputted in synchronization with the respective rises of complementary clock signals. Therefore, in the SDRAM and the DDR-SDRAM, power supply noise is more liable to occur than in the conventional DRAM. Besides, the voltage drops due to increases in current which flows through power supply line and ground line. In consequence, a power supply voltage VDD and a ground voltage VSS are liable to shift. Concretely, the power supply voltage VDD and the ground voltage VSS respectively differ at distant positions within a chip.
By way of example, in a case where the ground voltage VSS has shifted toward a plus side in the input buffer
1
shown in
FIG. 1
, the voltage V
1
of the node N
1
rises as indicated by a broken line in FIG.
4
. The supply current IC which is fed to the differential amplifier
3
decreases due to the rise of the voltage V
1
, so that the speed of the differential amplification of the input signals VIN
1
, VIN
2
lowers. This results in the problem that the output timing of the output signal OUT lags as indicated by a broken line.
On the other hand, in a case where the ground voltage VSS has shifted toward a minus side, the voltage V
1
of the node N
1
falls as indicated by a dot-and-dash line. The supply current IC which is fed to the differential amplifier
3
increases due to the fall of the voltage V
1
. This incurs the problem that the output timing of the output signal OUT advances as indicated by a dot-and-dash line.
As a result, the timing margin of the circuitry narrows to make the timing design thereof difficult.
Also in the input buffer
9
shown in
FIG. 2
, when the power supply voltage VDD has shifted, problems similar to the above occur to narrow the timing margin of the circuitry.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a constant-current generator whose supply current does not fluctuate even when a ground voltage VSS or a power supply voltage VDD has shifted.
Another object of the present invention is to provide a differential amplifier whose amplifying speed does not fluctuate even when a ground voltage VSS or a power supply voltage VDD has shifted.
Still another object of the present invention is to provide a semiconductor integrated circuit which includes a differential amplifier free from the fluctuation of the amplifying speed.
According to one of the aspects of the constant-current generator in the present invention, the generator comprises a bias transistor whose drain and gate are connected to each other, and an outputting transistor. The threshold voltage of the outputting transistor is smaller than that of the bias transistor. The outputting transistor has the same source voltage and the same gate voltage as those of the bias transistor. Therefore, the gate-to-source voltages of the outputting transistor and the bias transistor are always kept equal. On the other hand,
Fujioka Shin-ya
Funyu Akihiro
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Nguyen Khanh Van
Pascal Robert
LandOfFree
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