Coded data generation or conversion – Analog to or from digital conversion – With particular solid state devices
Reexamination Certificate
2000-02-22
2002-01-08
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
With particular solid state devices
C341S144000, C323S315000
Reexamination Certificate
active
06337644
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image processing apparatus, such as a fast video graphic controller for use in a digital television, a graphic display, etc., or a VGA-, SVGA-, or XGA-compatible video projector graphic controller. More particularly, the invention relates to a digital-to-analog conversion circuit built in the above type of image processing apparatus, i.e., to a structure of a semiconductor apparatus for implementing high-precision analog output, which is important for improving the quality of image display.
2. Description of Related Art
An image processing apparatus includes a digital-to-analog conversion circuit (hereinafter referred to as the “DAC”) for converting digital image data having individual colors, such as red, green, and blue, into analog data to be displayed on, for example, a CRT or a liquid crystal display unit.
This DAC is provided with a constant-current generating circuit for generating a certain constant current based on a reference voltage. The constant-current generating circuit has a basic-capacitance transistor and a transistor having a channel width of a ratio which is an integral multiple of the width of the basic-capacitance transistor. By a combination of the above-mentioned two transistors, a constant-current generating circuit for use in a current-addition-type DAC is formed. The basic-capacitance transistor, and the transistor which is designed to have an integral multiple of the capacitance of the basic-capacitance transistor, are provided as one set for the constant-current generating circuit. By combining a plurality of this set, weights are assigned to multibit digital input data. In this manner, the current-addition-type DAC is formed by combining a plurality of sets of current generating transistors having a capacitance according to “bit-weighting”.
FIG. 6
illustrates the layout of a conventional DAC having a plurality of sets of constant-current generating circuits, each having one basic-capacitance transistor and one transistor which is designed to have an integral multiple of the capacitance of the basic-capacitance transistor. Numeral
601
indicates a constant-current generating circuit having one set of the above transistors.
FIG. 7
illustrates the layout of a constant-current generating circuit having one set of the above transistors for use in a conventional DAC.
For simple description, a constant-current generating circuit whose output capacitance is
1
and a constant-current generating circuit whose output capacitance is 8 will be taken as examples of the circuit configuration.
A conventional DAC, in particular, an analog circuit, is formed of, as illustrated in
FIG. 6
, the constant-current generating circuits
601
and an analog switch
602
which determines by digital input whether data is output or discarded (not output). The number of sets of constant-current generating circuits
601
is determined by the number of bits of digital input and, basically, three output channels, each channel having the configuration shown in
FIG. 6
, are provided so as to correspond to analog channels of the individual colors, such as R (red), G (green), and B (blue).
Hitherto, the peripheral portion of the constant-current generating circuit, which determines the precision of digital-to-analog conversion of the DAC, is always exposed and is placed adjacent to external MOS transistors, though this varies according to the layout of the surrounding MOS transistors.
However, the following problem occurs in the configuration layout of the constant-current generating circuit having one set of the transistor having a capacitance of 1 and the transistor having a capacitance of 8, as shown in FIG.
7
. Although the size ratio of the two transistors is 1:8, the MOS transistor having a capacitance of 8 is vulnerable to variations generated in the device forming process. Thus, the uniformity of devices is not guaranteed.
In the constant-current generating circuit shown in
FIG. 7
, a source electrode
702
, which serves as a current generating source, is used together with the adjacent constant-current generating transistor. Moreover, since the source electrode
702
itself is placed farther inward than the device, uniformity of the source resistance, which is one factor for stably generating a constant current, is achieved.
Concerning drain electrodes
701
for extracting an output current, however, some drain electrodes
701
are located farther inward than the corresponding constant-current generating transistors, and some drain electrodes
701
are placed farther outward than the corresponding constant-current generating transistors. Accordingly, variations of the drain capacitance, the drain resistance, etc., are produced. Such variations cannot be eliminated even by swapping the positions of the drains and sources shown in
FIG. 7
, thereby failing to achieve uniformity of the capacitance and the resistance.
Also, the MOS transistors located at the upper and lower edges are positioned at the peripheral portion of the constant-current generating circuit shown in FIG.
6
. Thus, in particular, the distribution of the pattern density when gate electrodes are formed, which causes variations of the gate length, cannot be ignored.
This is because the distribution of the pattern density causes a loading effect in the gate-electrode forming process, which generates variations of the pattern dimensions after etching.
As discussed above, according to the conventional art, a constant current cannot be stably generated due to the following reasons.
1. The uniform formation of a pattern based on the basic-capacitance transistors cannot be achieved. That is, the drain resistance, the source resistance, and so on, are not consistent.
2. Since the peripheral portion is exposed, variations of the gate length and the threshold voltage (Vth) of the constant-current generating transistors are encouraged.
SUMMARY OF THE INVENTION
3. Even by combining a plurality of constant-current generating circuits, each having a set of transistors, positional uniformity cannot be achieved, thereby failing to stabilize a constant current within one channel.
In view of the above background, it is an object of the present invention to provide a circuit for stably generating constant current in a DAC for use in an image processing apparatus so as to implement high-precision output, which is important for the quality of image display.
A constant-current generating circuit of the present invention includes a plurality of current-generating transistors, each having a gate electrode controlled by a reference voltage, a source electrode connected to a current-generating source, and a drain electrode for extracting an output current generated by the reference voltage. The plurality of current-generating transistors are disposed in the form of a SEA OF GATES.
The SEA OF GATES (hereinafter referred to as “SOG”) is a gate array having a structure in which transistors are mounted on the entire chip, and is also referred to as a channel-less type or a free channel. Normally, according to the SOG technique, random logic, such as a gate array, is formed by changing the pattern data of metal, contacts, and via-holes in the metal wiring process.
This technique offers the advantage of suppressing variations generated during the formation of devices, since transistors, which are individual basic devices, are arranged in a regular order. A current-addition-type DAC, such as the one of this invention, has a plurality of current-generating transistors. Accordingly, the circuit configuration can be established even by combining a plurality of basic-capacity transistors arranged in the form of the SOG. Thus, by utilizing the SOG technique for the constant-current generating circuit, the pattern of the basic-capacitance transistors can be made uniform, thereby obtaining a stable constant-current output.
According to the constant-current generating circuit of the present invention, the plurality of current-generating transistors may
Oliff & Berridg,e PLC
Seiko Epson Corporation
Williams Howard L.
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