Electricity: power supply or regulation systems – Self-regulating – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2000-01-21
2001-03-13
Berhane, Adolf Deneke (Department: 2838)
Electricity: power supply or regulation systems
Self-regulating
Using a three or more terminal semiconductive device as the...
Reexamination Certificate
active
06201380
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a constant current/constant voltage generation circuit provided in a semiconductor integrated circuit device, and more particularly, to the structure of a circuit generating a bias current for generating a constant voltage.
2. Description of the Background Art
A semiconductor integrated circuit device includes an internal voltage generation circuit for internally generating a reference voltage of a prescribed level. The internal voltage generation circuit internally generates the reference voltage, thereby enabling reduction of a pin count and generation of a reference voltage of the optimum level depending on the operating characteristics of an internal circuit.
FIG. 1
illustrates the structure of a conventional reference voltage generation circuit. Referring to
FIG. 1
, the conventional reference voltage generation circuit includes a constant voltage generation circuit
1
generating a constant voltage V
1
not dependent on a power supply voltage Vcc, and a reference voltage production circuit
2
producing an output voltage Vout when activated in accordance with the constant voltage V
1
from constant voltage generation circuit
1
.
Constant voltage generation circuit
1
includes a constant current source
1
a
connected between a power supply node and a node N
1
for supplying a constant current, and an N-channel MOS transistor
1
b
converting the constant current from constant current source
1
a
to the voltage V
1
. MOS transistor
1
b
has a gate and a drain connected to node N
1
and operates in a saturation region to set the gate and drain voltages so as to receive and discharge the constant current supplied from constant current source
1
a
as a drain current. Therefore, the voltage V
1
outputted to node N
1
reaches a constant level not dependent on power supply voltage Vcc.
Reference voltage production circuit
2
includes an N-channel MOS transistor
2
a
connected between a node N
2
and a ground node with a gate thereof connected to node N
1
, a P-channel MOS transistor
2
b
connected between a power supply node and a node N
4
and receiving a mode switching signal &phgr;A at a gate thereof, a P-channel MOS transistor
2
c
connected between node N
4
and node N
2
with a gate thereof connected to node N
2
, a p-channel MOS transistor
2
d
connected between node N
4
and a node N
3
with a gate thereof connected to node N
2
and an N-channel MOS transistor
2
e
connected between node N
3
and a ground node with a gate thereof connected to node N
3
.
MOS transistor
2
a
forms a current mirror circuit with MOS transistor
1
b
of constant voltage generation circuit
1
, while MOS transistors
2
c
and
2
d
form another current mirror circuit. MOS transistor
2
e
converts a current supplied from MOS transistor
2
d
to a voltage and produces the output voltage Vout.
Mode switching signal &phgr;A is a control signal for activating/inactivating the operation of the reference voltage generation circuit generating the output voltage Vout. Mode switching signal &phgr;A is driven to an active low level when activating the operation of generating the reference voltage Vout, and the output voltage Vout is produced in accordance with the voltage V
1
on node N
1
. In an inactive state, mode switching signal &phgr;A is set high at the level of power supply voltage Vcc, MOS transistor
2
b
is turned off and current supply to MOS transistors
2
c
and
2
d
is stopped. In this state, node N
2
is discharged to a ground voltage level through MOS transistor
2
a
, while node N
3
is also discharged to the ground voltage level through MOS transistor
2
e.
The constant voltage generation circuit
1
is simply required to supply the constant voltage V
1
to the gate of MOS transistor
2
a
, and consumes an extremely small current. On the other hand, reference voltage production circuit
2
supplies the reference voltage Vout to a circuit such as a compare circuit or a constant current source. Therefore, the reference voltage production circuit
2
has relatively large current driving capability so as to stably drive a relatively large output load. When MOS transistors
1
b
and
2
a
are identical in size to each other, the drain voltage of MOS transistor
2
a
(i.e., the voltage of node N
2
) is also equal to the voltage V
1
. When MOS transistors
2
c
and
2
d
are equal in size to each other, the currents of nodes N
2
and N
3
are equal in magnitude to each other through operation of the current mirror circuit formed by MOS transistors
2
c
and
2
d
. Therefore, the level of the output voltage Vout is equal to that of voltage V
1
(when MOS transistors
2
a
and
2
e
are equal in size to each other). The term “size” indicates the ratio W/L of a gate width W to a gate length L of the MOS transistors.
The reference voltage Vout can be produced in response to the operation of the circuit using the output voltage Vout by selectively activating/inactivating the reference voltage production circuit
2
through mode switching signal &phgr;A, thereby reducing current consumption.
FIG. 2
illustrates voltage waveforms in mode switching on respective nodes of the reference voltage generation circuit shown in FIG.
1
. In a standby state, mode switching signal &phgr;A is set high, MOS transistor
2
b
is turned off, and the voltage on node N
2
and the output voltage Vout go down to the ground voltage. Constant voltage generation circuit
1
regularly operates, and node N
1
is set to voltage V
1
responsive to the constant current from constant current source
1
a.
At a time ta, mode switching signal &phgr;A is set to an active low level and MOS transistor
2
b
is turned on. Thus, a current is supplied to node N
2
through MOS transistor
2
c
, to raise the voltage level of node N
2
. MOS transistor
2
a
has a parasitic capacitance Cpr provided by a parallel body of a gate capacitance formed by a gate insulative film and a fringe capacitance formed between a peripheral portion of a source/drain region thereof and a gate electrode thereof. This parasitic capacitance Cpr is connected between node N
2
and node N
1
. When the voltage level of node N
2
is raised, therefore, this voltage rise is transmitted to node N
1
due to a coupling effect of parasitic capacitance Cpr, to raise the level of the constant voltage V
1
on node N
1
. When the level of the voltage V
1
on node N
1
is raised, the amount of current flowing through MOS transistors
2
c
and
2
a
is increased to increase the amount of current flowing through MOS transistors
2
d
and
2
e
, thereby raising the level of the reference voltage Vout outputted from node N
3
. The voltage of node N
2
is raised toward a prescribed level in response to the current supplied through MOS transistors
2
c
and
2
a
. Even if the voltage level of node N
2
is stabilized, the voltage V
1
of node N
1
is at a raised level due to the coupling effect of parasitic capacitance Cpr and a relatively long time is required until MOS transistor
1
b
discharges the voltage of node N
1
. In a period T when the voltage level of node N
1
is higher than a predetermined level, therefore, the level of the reference voltage Vout is also high and a circuit receiving the reference voltage Vout cannot stably operate during this period T. Therefore, when the mode switching signal &phgr;A is used for switching the standby state and an active state, for example, an activated internal circuit operates after a lapse of the time T from the time ta in a practical use. Thus, the timing for starting the operation of the internal circuit is disadvantageously delayed.
Such instability of the reference voltage in mode switching in the reference voltage generation circuit having the aforementioned mode switching function also takes place in a structure other than the current mirror type reference voltage generation circuit in general.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a reference voltage generation circuit capable of stably
Ikeda Yutaka
Tsujino Mitsunori
Berhane Adolf Deneke
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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