Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Patent
1999-07-27
2000-05-09
Thomas, Tom
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
438401, 438462, H01L 23544
Patent
active
060607874
ABSTRACT:
Provided is a method and composition for reducing the rate of, and rendering more uniform the oxidation of alignment mark trench side walls by CMP slurry accumulating in an alignment mark trench during CMP processing. In a preferred embodiment, a nucleation layer of tungsten having an equiaxed grain structure with fine grain size and conformity is deposited over a conventionally applied bulk tungsten layer prior to commencing CMP operations. The fine grain size and equiaxed grain structure of this nucleation layer make it more resistant and more uniform in response to slurry attack. As a result, the tungsten trench profile remains a consistent and reliable alignment mark.
REFERENCES:
patent: 3859143 (1975-01-01), Krebs
patent: 5002902 (1991-03-01), Watanabe
patent: 5055423 (1991-10-01), Smith et al.
patent: 5064683 (1991-11-01), Poon et al.
patent: 5089438 (1992-02-01), Katz
patent: 5169685 (1992-12-01), Woodruff
patent: 5270255 (1993-12-01), Wong
patent: 5298458 (1994-03-01), Mieno et al.
patent: 5312512 (1994-05-01), Allman et al.
patent: 5329334 (1994-07-01), Yim et al.
patent: 5464031 (1995-11-01), Buley et al.
patent: 5503962 (1996-04-01), Caldwell
patent: 5532520 (1996-07-01), Haraguchi et al.
patent: 5554561 (1996-09-01), Plumton
patent: 5563090 (1996-10-01), Lee et al.
patent: 5612558 (1997-03-01), Harshfield
patent: 5618381 (1997-04-01), Doan et al.
patent: 5672385 (1997-09-01), Jimba et al.
patent: 5686761 (1997-11-01), Huang et al.
patent: 5700383 (1997-12-01), Feller et al.
patent: 5701013 (1997-12-01), Hsia et al.
patent: 5702981 (1997-12-01), Maniar et al.
patent: 5705080 (1998-01-01), Leung et al.
patent: 5717250 (1998-02-01), Schuele
patent: 5719495 (1998-02-01), Moslehi
patent: 5840366 (1998-11-01), Mizuno et al.
patent: 5847468 (1998-12-01), Nomura et al.
patent: 5877562 (1999-03-01), Sur et al.
patent: 5972793 (1999-10-01), Tseng
Chao Keith K.
Dou Shumay X.
Zhao Joe W.
LSI Logic Corporation
Owens Douglas W.
Thomas Tom
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