Consistency ensuring system for the contents of a cache memory

Details Consistency ensuring system for the contents of a cache memory Consistency ensuring system for the contents of a cache memory

1988-10-28

1991-04-23

Fleming, Michael R.

Boots, shoes, and leggings

3642281, 36424341, 36424344, G06F 1516

Patent

active

050104756

ABSTRACT:
A consistency ensuring system has at least one main memory and a plurality of processors each having a corresponding instruction cache memory and operand cache memory. Each of the plurality of processors includes a flush address array device, an address converting device, a signal generating device and a flush address array invalidating device. The flush address array device maintains a copy of an address array to be looked up for invalidating a block of data in the cache memories of the corresponding processor in response to storing a corresponding block of data into the main memory from another processor. The address converting device converts a virtual address to a real address and updates a page table word after address conversion and storage of the updated page table word in the main memory but not in the corresponding cache memories. The signal generating device generates a page table word store notice signal when the address converting device stores the updated page table into the main memory. The flush address array invalidating device invalidates the data of the corresponding block in the cache memories of the corresponding processor in response to the the page table word store notice signal and a real memory address of the page table word from the corresponding process.

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