Consecutive identical digit suppression system in a digital comm

Details Consecutive identical digit suppression system in a digital comm Consecutive identical digit suppression system in a digital comm

1982-04-19

1985-02-26

Smith, Jerry

Excavating

375 22, 455608, H03K 526

Patent

active

045021430

ABSTRACT:
An encoder for suppression of a consecutive identical digit in a digital transmission system has been found for facilitating the reproduction of a clock signal for regenerating reception data, and keeping the average signal level constant. According to the present invention, a single bit (x) is inserted for every predetermined number (m) of input digits, and said insertion bit is a complement of a digit of previous k bits where k is an integer satisfying 1.ltoreq.k.ltoreq.m. Preferably, the value k is 1. The present invention is useful for digital communication higher than 100 Mbits/second, in particular, in optical communication.

REFERENCES:
patent: 4034406 (1977-07-01), Tsuchiya et al.
patent: 4131915 (1978-12-01), Nakagome et al.
patent: 4161719 (1979-07-01), Porikh et al.
patent: 4189621 (1980-02-01), Scott et al.
patent: 4262309 (1981-04-01), Yamaguchi et al.
patent: 4347617 (1982-08-01), Murano et al.
Hiroyuki Kasai et al., "PCM Jitter Suppression by Scrambling", IEEE Transactions on Communications, vol. COM-22, No. 8, Aug. 1974.

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