Consecutive addressing of a semiconductor memory

Details Consecutive addressing of a semiconductor memory Consecutive addressing of a semiconductor memory

1981-07-23

1984-01-31

Stellar, George G.

Static information storage and retrieval

Addressing

Sequential

G11C 700, G11C 800

Patent

active

044293755

ABSTRACT:
A high speed memory device comprises memory cells arrayed in rows and columns, a row decoder for selecting the rows, a column decoder for selecting the columns, a shift register arranged in parallel with the column decoder, and control means for operatively enabling the shift register, in which consecutive access to a plurality of memory cells belonging to the same selected row can be performed from the column address designated by the column decoder.

REFERENCES:
patent: 3930239 (1975-12-01), Salters et al.

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