Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-02-01
2001-10-02
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S076110, C324S654000, C324S658000, C714S727000
Reexamination Certificate
active
06297643
ABSTRACT:
The invention relates to a method of testing a signal path in a circuit, the method comprising the step of applying a test signal to a terminal of the signal path. The invention further relates to a testable circuit and an integrated circuit for implementing such a method.
For testing signal paths connected to integrated circuits (ICs) in an IC assembly such as a printed circuit board or a multi-chip module, in-circuit techniques have been widely used. Due to the trend of miniaturization of electronic components this approach is getting less feasible. A preferred approach is to use special ICs comprising dedicated test hardware for in a test mode testing the signal paths. For digital signal paths, providing connection between digital sections of ICs, a particularly successful example of such an approach is the boundary-scan approach, as defined by the IEEE Std. 1149.1. The boundary-scan approach amounts to driving a first IC pin at one end of such a signal path to a high or a low level and sensing a second IC pin at an other end of the signal path. As in digital assemblies the digital signal paths usually are plain wires, and the signal levels are DC voltage levels, the signals at both ends should be DC voltage levels. To facilitate the propagation of input signals to interior nodes of the IC, and the propagation of output signals from interior nodes of the IC, a series of boundary-scan cells are used. The input test pattern is provided to each cell by serial shifting from an input pin that contains the appropriate test pattern to the series of boundary scan cells. The input test pattern, which is now contained in the boundary scan cells, is then applied to the interior input nodes. The resultant states of select interior nodes, produced by the application of the test pattern, are provided to the scan cells. The contents of these scan cells are serial shifted to an output pin of the IC. The series of DC voltage levels from the output pin are compared to an expected output pattern, based on the input test pattern. In this way, faults in the signal path, such as open and short connections, can be easily detected.
Analog signal paths, however, often comprise analog circuits such as filters. The boundary-scan approach can not be used for testing such signal paths, as driving an input of, for example, a high-pass filter with a DC voltage level will not necessarily result in the same voltage at the time of capture on an output pin thereof. A method for testing such signal paths is described in WO 97/14974 (corresponding to U.S. patent application Ser. No.
08/734,009).
According to the known method, a time-varying test signal is generated at an input of the signal path, whereas at a test point that is coupled to an output of the signal path, a response signal is detected. Faults in the signal path can thus be detected on the basis of the temporal behaviour of the response signal.
It is an object of the invention to provide a method as specified in the preamble, which can be more generally applied than the known method. To this end, a method according to the invention is characterized in that the method further comprises the step of evaluating a response signal on the same terminal as to which the test signal is applied. Thus, use is made of the fact that applying a test signal to the terminal of a signal path produces at the same terminal an effect characterizing that signal path. This effect, having the form of a response signal, can be evaluated.
The invention is particularly useful when only one terminal of the signal path to be tested is available for testing. This is the case, for example, with a widely used element as a decoupling capacitance between an IC pin and a supply line, e.g. a ground line. When testing for the presence of such a capacitance from within the IC, the capacitance can only be accessed via the IC pin. The known method can not be used for testing such an analog signal path, as it requires both an input and an output of the signal path. A further example is the case in which the signal path to be tested at one of its ends is connected to an IC or other device that is not equipped with test hardware in conformity with the boundary-scan approach or with the above known method. In both cases the signal path can be tested with the method of the invention.
The response signal could completely or partially coincide with the test signal. Alternatively, the test signal and the response signal are distinct signals. This is the case, for example, when the test signal is applied in a first phase for pumping energy into the signal path, at the same time the energy being stored in reactive components of the signal path such as capacitances and inductances, and in a subsequent second phase the energy is released via the terminal, thereby forming the response signal. Anyhow, only one terminal of the signal path to be tested has to be accessible.
The outcome of the evaluation, and therefore of the test, could be a binary value indicating whether or not the signal path produced a response signal with an expected behaviour. Hereto, level detection methods could be used, detecting, for example, whether or not the response signal within some time interval reaches a certain level or whether or not the response signal at a certain moment still has a certain level. Alternatively, the outcome of the evaluation is a more comprehensive qualification of the signal path in terms of circuit parameters such as resistance, capacitance, attained voltage level, etc.
In some cases, it is not practical to use the aforementioned level detection method approach and detect whether the response signal reaches a certain level. When the response signal is weak, for example, this would require a rather precise detection method. In an embodiment of the method according to the invention the evaluating step comprises deriving a secondary signal that comprises an integrated version of the response signal and detecting whether the secondary signal reaches a certain level. As in a value of the secondary signal at a certain moment the characteristics of the signal path have accumulated, this signal can be a more reliable indication of the signal path and therefore be a more suitable signal for use with a level detection method. This aspect of the invention is particularly useful for small, diminishing response signals, such as a signal produced by a discharging capacitance. The integration produces a secondary signal with a positive slope, the amplitude of the secondary signal being a measure of the capacitance. It is not required, however, that the secondary signal is exactly an integrated version of the response signal. It suffices that the value of the secondary signal at a certain moment is related to the values of the response signal within a preceding interval. Therefore, the secondary signal is said to comprise an integrated version of the response signal.
Advantageously, the method according to the invention is applied to testing a signal path in an IC assembly, in which case the above circuit is the IC assembly, the above signal path is external to the ICs thereof, and the above terminal is an IC pin.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
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patent: WO9714974 (1997-04-01), None
De Jong Franciscus G. M.
de Wilde Johannes
Muris Mathias N. M.
Schuttert Rodger F.
Deb Anjan K.
Metjahic Safet
U.S. Philips Corporation
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