Multiplex communications – Channel assignment techniques – Details of circuit or interface for connecting user to the...
Reexamination Certificate
1999-10-01
2004-07-13
Hsu, Alpus H. (Department: 2139)
Multiplex communications
Channel assignment techniques
Details of circuit or interface for connecting user to the...
C370S445000, C370S461000
Reexamination Certificate
active
06763034
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to connection ports for interconnecting functional modules in an integrated circuit. In particular the present invention relates to connection ports for interconnecting respective functional modules to a packet router in an integrated circuit.
BACKGROUND OF THE INVENTION
Computer systems and integrated circuit processors exist which implement transactions with the dispatch and receipt of packets. Request packets define an operation to be performed and response packets indicate that a request has been received and whether or not the operation defined in the request packet has been successfully carried out. The integrated circuit processor can comprise a plurality of functional modules connected to a packet router for transmitting and receiving the request and response packets. Each functional module is connected to the packet router via a respective port. The increasing ability to incorporate a greater number of more complex modules on a single chip means that it is now possible to integrate a high performance CPU with a number of complex modules using a high performance bus in a system on a chip. Generally, the design process is such that the architecture of a processor is designed and the functional modules which are required are determined. Then, ports have to be designed for the functional modules to connect the functional modules to a packet router of the integrated circuit.
The complexity of the port depends on the complexity and functionality of the functional module which is to be attached to the packet router by the port. In principle therefore it is either necessary to design a port to match the functionality of each functional module, or to constrain the functional modules which can be connected to a packet router by the ports which have been designed.
It is an aim of the present invention to provide connection ports with enhanced functionality which are preferably based around a common port primitive. This simplifies port design and selection and also allows the common packet protocol to be used for communication of packets across the packet router.
SUMMARY OF THE INVENTION
According to a first aspect of the invention there is provided a target port for a functional module in an integrated circuit system, the target port comprising: an input buffer for holding a plurality of request packets received from a packet router of the integrated circuit system; control circuitry for selecting a request packet held in said input buffer for supply to the functional module to implement the operation defined in the request packet; and an output buffer for holding a plurality of response packets, each response packet being generated by the functional module responsive to receipt of a request packet; wherein each request packet includes an indicator of the source of the packet and a transaction identifier uniquely identifying the transaction in which the packet is engaged and wherein said response packets use the source identifier as a destination indicator for identifying the destination of the response packet, and also convey said unique transaction identifier.
Thus, initiators can dispatch requests to implement a series of transactions without having to wait for the first transaction to be completed before dispatching a request for the next transaction. This ability to implement out of order transactions can significantly improve the performance of the system.
The control circuitry can be arranged to determine whether a request packet formulated by the functional module forms part of a simple transaction involving a single request packet or a compound transaction involving a plurality of request packets and, in the case of a compound transaction, cause a lock signal to be supplied for all request packets involved in the compound transaction save the last packet, said lock signal being supplied on signal lines in both said first and second group.
The lock signal can be used by the system control unit to control arbitration of packets on a packet router so that all request packets involved in a compound transaction can be conveyed in an uninterrupted fashion. The transfer of the lock signal on the signal lines conveying packet information from the initiator port allows the lock signal to be conveyed to a target module to advise the target module that an uninterrupted sequence of request packets is to be transmitted.
Priority information conveyed with the request packet can be copied into the response packet.
The control circuitry can be operable to generate a transfer request signal a destination indicator to request transfer of a packet from the initiator port onto the packet router.
The port can include packet framing circuitry for generating an end of packet signal to be conveyed on the first group of outgoing signal lines. It is possible however for such packet framing circuitry to form part of the functional module to which the port is connected such that the port conveys the end of packet information by a “dumb” wire.
According to the described packet protocol each request packet includes an opcode field identifying an operation to be performed by the transaction.
Another aspect of the invention provides an integrated circuit system comprising: a plurality of initiator functional modules; a plurality of target functional modules; a packet router to which said plurality of initiator functional modules and target functional modules are connected via respective initiator ports and target ports; wherein each initiator module is operable to generate a sequence of requests relating to respective transactions without waiting for a response to a first request in the sequence before issuing a subsequent request in the sequence and wherein each target port comprises an input buffer for queuing a sequence of incoming requests received from the packet router from said initiator modules and control circuitry for selecting requests from the input buffer for implementation by the attached functional module, the target functional module being operable to generate a response each time a request has been handled by the target functional module.
Another aspect of the invention provides a target port for connecting a target functional module to a packet router, the target port comprising: a first group of incoming signal lines for receiving packet information from the packet router; a second group of outgoing signal lines for conveying control signals from the port to a system control unit; a third group of outgoing signal lines for conveying packet information from the target functional module to the packet router, wherein said first group includes a signal line conveying a lock signal indicating that a request packet conveyed by the first group of signal lines forms part of a compound transaction involving a plurality of request packets, the target port further comprising: control circuitry responsive to receipt of said lock signal to generate a response lock signal when a response packet is conveyed responsive to a request packet in which the lock signal was set.
The packet information can include an opcode field which, for a response packet, distinguishes between an ordinary response and an error response. An ordinary response is conveyed when the requested operation has been effected. An error response is conveyed when the requested operation cannot be effected by the target functional module.
A further aspect of the present invention provides a target port for connecting a target functional module to a packet router, the target port comprising: a first group of incoming signal lines for conveying packet information from the packet router to the target functional module; a second group of outgoing signal lines for conveying control signals from the port to a system control unit; a third group of outgoing signal lines for conveying packet information to the packet router; and control circuitry operable to generate a priority signal to be conveyed by signal lines in the second and third group, said priority signal relating to a response
Carey John A.
Hasegawa Atsushi
Jones Andrew M.
Hsu Alpus H.
Jorgenson Lisa K.
Kubida William J.
STMicroelectronics Ltd.
Tran Thien
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