Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1997-06-30
2001-01-23
Young, Lee (Department: 3729)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S260000, C029S830000
Reexamination Certificate
active
06177636
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates, generally, to interconnecting microelectronic devices and supporting substrates, and more particularly relates to an apparatus and a method of interconnecting microelectronic devices to supporting substrates using subtractively created members.
BACKGROUND OF THE INVENTION
Complex microelectronic devices such as modem semiconductor chips require many hundreds of input and output connections to other electronic components. These device connections are generally either disposed in regular grid-like patterns, substantially covering the bottom surface of the device (commonly referred to as an “area array”) or in elongated rows extending parallel to and adjacent each edge of the device's front surface. The various prior art processes for making the interconnections between the microelectronic device and the supporting substrate use prefabricated arrays or rows of leads/discrete wires, solder bumps or combinations of both, such as with wire bonding, tape automated bonding (“TAB”) and flip/chip bonding.
In a wirebonding process, the microelectronic device may be physically mounted on a supporting substrate. A fine wire is fed through a bonding tool and the tool is brought into engagement with a contact pad on the device so as to bond the wire to the contact pad. The tool is then moved to a connection point of the circuit on the substrate, so that a small piece of wire is dispensed and formed into a lead, and connected to the substrate. This process is repeated for every contact on the chip. The wire bonding process is also commonly used to connect the die bond pads to lead frame fingers which are then connected to the supporting substrate.
In a tape automated bonding (“TAB”) process, a dielectric supporting tape, such as a thin foil of polyimide is provided with a hole slightly larger than the microelectronic device. An array of metallic leads is provided on one surface of the dielectric film. These leads extend inwardly from around the hole towards the edges of the hole. Each lead has an innermost end projecting inwardly, beyond the edge of the hole. The innermost ends of the leads are arranged side by side at a spacing corresponding to the spacing of the contacts on the device. The dielectric film is juxtaposed with the device so that the hole is aligned with the device and so that the innermost ends of the leads will extend over the front or contact bearing surface on the device. The innermost ends of the leads are then bonded to the contacts of the device, typically using ultrasonic or thermocompression bonding, and the outer ends of the leads are connected to external circuitry.
In both wire bonding and conventional tape automated bonding, the pads on the substrate are arranged outside of the area covered by the chip, so that the wires or leads fan out from the chip to the surrounding pads. The area covered by the entire assembly is considerably larger than the area covered by the chip. This makes the entire assembly substantially larger than it otherwise would be. Because the speed with which a microelectronic assembly can operate is inversely related to its size, this presents a serious drawback. Moreover, the wire bonding and tape automated bonding approaches are generally most workable with chips having contacts disposed in rows extending along the edges of the chip. They generally do not allow use with chips having contacts disposed in an area array.
In the flip-chip mounting technique, the front or contact bearing surface of the microelectronic device faces towards the substrate. Each contact on the device is joined by a solder bond to the corresponding contact pad on the supporting substrate, as by positioning solder balls on the substrate or device, juxtaposing the device with the substrate in the front-face-down orientation and momentarily reflowing the solder. The flip-chip technique yields a compact assembly, which occupies an area of the substrate no larger than the area of the chip itself. However, flip-chip assemblies suffer from significant problems when encountering thermal stress. The solder bonds between the device contacts and the supporting substrate are substantially rigid. Changes in the relative sizes of the device and the supporting substrate due to thermal expansion and contraction in service create substantial stresses in these rigid bonds, which in turn can lead to fatigue failure of the bonds. Moreover, it is difficult to test the chip before attaching it to the substrate, and hence difficult to maintain the required outgoing quality level in the finished assembly, particularly where the assembly includes numerous chips.
As the number of interconnections per microelectronic device increases, the issue of interconnection planarity continues to grow as well. If the interconnections are not planar with respect to each other, it is likely that many of the interconnections will not electrically contact their juxtaposed contact pads on a supporting substrate, such as a standard printed wiring board. None of the above described techniques provides a cost effective interconnection scheme which guarantees the planarity of the interconnections so that each is assured of making an electrical contact with the contact pads on the opposed supporting substrate.
Numerous attempts have been made to solve the foregoing interconnection problems. An interconnection solution put forth in U.S. Pat. No. 4,642,889, entitled “Compliant Interconnection and Method Therefor” issued Apr. 29, 1985 to Grabbe creates an interconnection scheme by embedding wires within each solder column/ball to reinforce the solder thereby allowing higher solder pedestals and more elasticity. Further interconnection solutions put forth include providing a combination of solder and high lead solder thereby allowing higher solder pedestals and more elasticity given the high lead content of the solder, as found in U.S. Pat. No. 5,316,788, entitled “Applying Solder to High Density Substrates” issued May 31, 1994 to Dibble et al. and U.S. Pat. No. 5,203,075 & 5,133,495, respectively issued on Apr. 20, 1993 and Jul. 28, 1992 to Angulas et al.
U.S. Pat. No. 4,955,523, entitled “Interconnection of Electronic Components” issued on Sep. 11, 1990 to Calomagno et al. puts forth a still further interconnection technique in which wires are wirebonded to the contact pads on a first surface, cut to a desired length and then attached to a second opposing surface by placing each of the wires in a “well” of conductive material, such as solder. While the wires then give a certain amount of compliancy to the structure, this technique encounters difficulties in controlling unwanted bending and electrical shorting of the wires prior to and during the coupling step in their respective solder wells. Similarly, U.S. Pat. No. 5,067,007, entitled “Semiconductor Device having Leads for Mounting to a Surface of a Printed Circuit Board” issued Nov. 19, 1991 to Kanji et al. discloses the use of stiff or deformable lead pins to increase the pin pitch and deal with problems stemming from thermal coefficient of expansion mismatches between the device and a printed circuit board. Besides the potential for bending and shorting of the pins as described above, the pins are individually attached to both the device and the printed circuit board by brazing or soldering making this a time consuming and less than optimum solution from a manufacturing point of view.
U.S. Pat. No. 4,067,104, entitled “Method of Fabricating an Array of Flexible Metallic Interconnects for Coupling Microelectronic Components” issued on Jan. 10, 1978 to Tracy uses an additive technique where the interconnections are created by providing a layer of photoresist, removing portions of the photoresist and depositing metal within the removed portions. By successively following this technique, a plurality of metalized columns are created and coupled to opposing contact pads on a supporting substrate by a suitable method, such as flip chip bonding, cold welding, diffusion bonding or melting. The photoresist is then
Chang Rick Kiltae
Lerner David Littenberg Krumholz & Mentlik LLP
Tessera Inc.
Young Lee
LandOfFree
Connection components with posts does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Connection components with posts, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Connection components with posts will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2501660