Connection and build-up technique for multichip modules

Details Connection and build-up technique for multichip modules Connection and build-up technique for multichip modules

1995-06-27

1996-09-17

Picardat, Kevin M.

Fishing, trapping, and vermin destroying

437180, 437183, 437189, 437203, 427 96, H01L 2160

Patent

active

055568122

ABSTRACT:
A method for manufacturing multichip modules having layer sequences made of dielectric material with conducting tracks embedded therein is characterized by the following features: (1) a temperature-resistant, base-resistant polymer having a dielectric constant .ltoreq.3 is used as a dielectric material, which is applied to a non-conductive substrate and serves as an edge boundary for currentless, autocatalytic build-up of the conducting tracks; (2) the dielectric material is provided with a layer made of material which is soluble in organic solvents (lift-off layer); (3) the dielectric material and the lift-off layer are structured in a single lithographic step, either a direct or an indirect structuring taking place and grooves having an aspect ratio .gtoreq.1 being formed in the dielectric material; (4) a metallic seed layer is applied to the dielectric material or rather to the lift-off layer through vapor deposition in a directed manner; (5) the lift-off layer is removed using an organic solvent; and (6) conducting tracks are created in the grooves through currentless metal deposition.

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