Congestion control mechanism in a network access device

Details Congestion control mechanism in a network access device Congestion control mechanism in a network access device

1999-06-03

2003-11-11

Nguyen, Steven (Department: 2665)

Multiplex communications

Data flow congestion prevention or control

C370S235000, C370S395430, C709S212000, C709S232000

Reexamination Certificate

active

06646985

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
Not Applicable
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
The present invention relates generally to the field of data networks, and in particular to network access devices that multiplex data from several incoming interfaces to a generally smaller number of outgoing interfaces.
Multiplexing network access devices, such as devices known as add/drop multiplexers, are used to concentrate network data traffic from multiple network segments onto a generally smaller number of higher-throughput network segments. In many networks, such as Asynchronous Transfer Mode (ATM) networks, incoming data frames (referred to as “cells” in ATM networks) are not necessarily transmitted on a higher-throughput segment immediately upon receipt. Consequently, the access device employs buffering in order to manage the forwarding of received frames to an output segment. Additionally, under certain traffic conditions, there may temporarily be insufficient bandwidth available on a higher-throughput segment to transmit all of the frames received from incoming network segments. During such periods, incoming frames are placed in buffers temporarily, until outgoing transmission bandwidth is available to transmit the frames. The use of buffers thus reduces the need to discard frames due to a temporary shortage of outgoing transmission bandwidth.
Various parameters affect the need for buffering in a network access device. These parameters include the relationship between the aggregate data rate of the lower-throughput segments, on the one hand, and the available transmission bandwidth on the higher-throughput segment, on the other hand. Additionally, the relationship between peak and average data rates is important. In a device in which the ratio of peak aggregate incoming data rate to peak outgoing data rate is high, for example on the order to 10:1 or greater, the buffers within the device may experience congestion when the lower-throughput segments are simultaneously bursting traffic to the device. This congestion can be reduced by limiting, a priori, the peak data rates allowed at the inputs from the lower-throughput segments. However, this approach generally has the effect of reducing the allowed average data rates as well. This approach can therefore result in relatively poor average device utilization. To improve average device utilization, it is desirable to permit a higher ratio of peak aggregate incoming data rate to peak outgoing data rate. This technique is referred to as “overbooking” of outgoing bandwidth. However, it is desirable to avoid the discarding of frames that might occur during peak periods in a device in which overbooking is utilized.
A device known as the AToM4 Segmentation and Reassembly (SAR) chip, available from Toshiba Inc. as part no. TC35854F, provides functions for implementing ATM User Network Interfaces (UNIs) in certain types of network access devices. The SAR function is required when non-ATM services are provided over ATM networks. For example, frame-based or packet-based services can be provided over ATM networks. It is necessary to segment variable-size frames or packets into several fixed-length ATM cells for transmission over the network, and then to reassemble the cells into frames at the receiving end. The AToM4 device includes features such as packet stream to ATM circuit selection, ATM Adaptation Layer (AAL) functions, segmentation and reassembly (SAR), and cyclic redundancy check (CRC) generation and checking. The AToM4 device also contains mechanisms to support traffic shaping, varieties of ATM flow control protocols, and Operations Administration and Maintenance (OAM) flows.
In particular, the AToM4 provides operation in accordance with a standard ATM flow-control scheme known as Generic Flow Control (GFC). The transmission of cells from the AToM4 is controlled in accordance with GFC signalling information appearing in cells received by the AToM4. ATM connections are divided into two categories: controlled and uncontrolled. In the AToM4, all connections for constant bit rate (CBR) and Variable Bit Rate (VBR) traffic are uncontrolled, and the rest of the connection types, e.g. Available Bit Rate (ABR) and Unspecified Bit Rate (UBR) are controlled.
A 4-bit GFC field appears in the header of ATM cells received by the AToM4. The AToM4 responds to different values in the GFC field to control the sending of cells. As described in the data sheet for the AToM4, it is contemplated that the AToM4 is flow-controlled by an ATM switch connected to the network access device in which the AToM4 resides. The switch exercises flow control by setting the GFC bits in ATM cells sent from the switch to the network access device. This flow control mechanism is used to prevent the network access device from contributing to undesirable congestion in the switch or other devices in the ATM network.
While the AToM4 SAR device provides useful functions required in certain network access devices, its design does not address the problem of buffer congestion within the network access device. Additionally, the flow-control functionality of the AToM4 has generally not been widely used, because the GFC protocol per se has not been widely used. Thus, prior network access devices have been burdened by the cost of unused functionality in the AToM4 device, as well as the cost of external logic for managing buffer congestion within the network access device.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, a mechanism for controlling the congestion of buffers in an ATM network access device is disclosed that exploits the flow-control capability of SAR devices such as the AToM4 device. The congestion control mechanism enhances efficiency by permitting the overbooking of buffers, while avoiding the undue discarding of ATM cells.
The congestion control mechanism includes SAR logic that sends and receives data units such as Asynchronous Transfer Mode (ATM) cells at an interface. The cells are transferred on ATM connections, including flow-controlled connections for which the sending of cells by the SAR logic is controlled in response to the settings of flow control bits appearing in the headers of ATM cells received by the SAR logic. Interface logic is coupled to the ATM interface of the SAR logic to transfer cells between the SAR logic and a switch fabric. The interface logic receives a congestion signal indicative of the level of fullness of a transmit buffer in the switch fabric. In response to the congestion signal, the interface logic sets the flow control bits in the headers of cells transferred to the SAR logic such that the cell transmission rate from the SAR to the switch fabric is maintained at a high average level while undesirable congestion in the transmit buffer is avoided. In particular, the interface logic withholds sending indications to the SAR logic that it is permitted to send cells on the flow-controlled connections during periods in which the congestion signal from the switch fabric is asserted, indicating that a predetermined threshold of transmit buffer fullness is exceeded. In a disclosed technique, a credit-based flow control protocol is employed, and the permission indications sent from the interface logic to the SAR logic are credit indications that enable the SAR logic to send additional cells.
In more particular aspects, the disclosed congestion control mechanism employs hysteresis in the setting of the flow control bits to avoid unstable operation that might arise from an excessively fast response to the congestion signal. The disclosed interface logic also generates idle cells when necessary to provide flow control commands to the SAR logic during periods in which no traffic-carrying cells are being transferred from the switch fabric to the SAR logic.
The disclosed technique distributes the buffering of ATM cells between the buffer in the switch fabric and buffers associated with the SAR logic. The probability of cell discard is reduced, while des

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