Configuring routing in mesh networks

Multiplex communications – Pathfinding or routing – Through a circuit switch

Reexamination Certificate

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C716S101000, C712S011000, C370S400000

Reexamination Certificate

active

08045546

ABSTRACT:
A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and enables transfer of data among the processor cores. An extension network connects input/output ports of the interconnection network to input/output ports of one or more peripheral devices, each input/output port of the interconnection network being associated with one of the processor tiles such that each input/output port of the interconnection network sends input data to the corresponding processor tile and receives output data from the corresponding processor tile. The extension network is configurable such that a mapping between input/output ports of the interconnection network and input/output ports of the one or more peripheral devices is configurable.

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