Configuring a programmable logic device

Details Configuring a programmable logic device Configuring a programmable logic device

2001-10-05

2003-02-25

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Substituting specified bit combinations for other prescribed...

C326S040000

Reexamination Certificate

active

06525678

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present invention generally relates to programmable logic devices (PLDs) and more particularly to a system and method of configuring PLDs.
2. Description of the Related Art
In general, a programmable logic device (PLD) is configured by loading configuration data onto the PLD. The configuration data is typically cleared from the PLD when the PLD is powered down. As such, the configuration data is typically stored in memory, and the PLD is configured each time the PLD is powered up.
The time required to configure a PLD can be limited either by the time required to read the configuration data from memory or by the time required to write the configuration data into the PLD, which ever takes longer. Additionally, as the complexity of PLDs increases, so does the size of the configuration data that is used to configure the PLDs.
The amount of time required to configure a PLD can be reduced by increasing the access rate of the memory used to store the configuration data. However, there is generally a correlation between the speed and the price of memory (i.e., a faster memory is typically more expensive than a slower one). Thus, reducing the amount of time to configure a PLD by using faster memory can increase the price of the system that contains the PLD.
SUMMARY
The present invention relates to a system and method of configuring programmable logic devices (PLDs). In accordance with one aspect of the present invention, the configuration data used to configure a PLD is compressed using a compression algorithm before being stored in memory. When the PLD is to be configured, the compressed configuration data is read from memory, decompressed, then loaded onto the PLD.


REFERENCES:
patent: 5563592 (1996-10-01), Cliff et al.
patent: 5768372 (1998-06-01), Sung et al.
patent: 5872529 (1999-02-01), Mejia
Ch. W. Bachman, “The Programmer as Navigator”, ACM Tutoring, vol. 16, No. 11, Nov. 1973, pp. 653-658.
Ch. W. Bachman, “Implementation Techniques for Data Structure Sets”, North-Holland Publishing Co 1974, pp. 147-279.
Ch. W. Bachman papers, 1951-1996, CBI 125, 35 pgs., www.cbi.umn.edu/inv/bachman.htm, downloaded Mar. 27, 2000.
M. Jakobsson, “On Compression Techniques for Indexed Files”, University of VAASA, Report A30, 1981, pp. 28-35.
M. Jakobsson, “Evaluation of a Hierarchical BIT-Vector Compression Technique”, Information Processing Letters, vol. 14, No. 4, pp. 147-149.
D. King, “The Binary Vector as the Basis of an Inverted Index File”, J. of Library Automation, vol. 7/4, Dec. 1974, pp. 307-314.
R. N. Williams, “Adaptive Data Compression”, Kluwer Academic Publishers, 1991, pp. 19-22.
IEEE Transactions on Information Theory, correspondence, Nov. 1965, pp. 399-401.

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