Configuring a multi-processor system

Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing

Reexamination Certificate

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C370S351000

Reexamination Certificate

active

08001266

ABSTRACT:
A source processing node communicates with a destination processing node though a channel that has bandwidth requirements and is uni-directional. The source processing node generates the channel to the destination processing node. The destination processing node then accepts the channel. The source processing node allocates a transmit buffer for the channel. The destination processing node also allocates a receive buffer for the channel. A source processing element writes data to the transmit buffer for the channel. A source network interface transmits the data from the transmit buffer of the source processing node over the channel. A destination network interface receives the data into the receive buffer for the channel. A destination processing element receives the data from the receive buffer.

REFERENCES:
patent: 4635261 (1987-01-01), Anderson et al.
patent: 4766569 (1988-08-01), Turner et al.
patent: 4766659 (1988-08-01), Cronenwett et al.
patent: 4783738 (1988-11-01), Li
patent: 4893311 (1990-01-01), Hunter et al.
patent: 5055997 (1991-10-01), Sluijter
patent: 5247689 (1993-09-01), Ewert
patent: 5258668 (1993-11-01), Cliff et al.
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5274581 (1993-12-01), Cliff et al.
patent: 5274782 (1993-12-01), Chalasani
patent: 5299317 (1994-03-01), Chen
patent: 5343406 (1994-08-01), Freeman et al.
patent: 5357152 (1994-10-01), Jennings, III et al.
patent: 5361373 (1994-11-01), Gilson
patent: 5414377 (1995-05-01), Freidin
patent: 5426378 (1995-06-01), Ong
patent: 5436574 (1995-07-01), Veenstra
patent: 5471628 (1995-11-01), Phillips
patent: 5488612 (1996-01-01), Heybruck
patent: 5517627 (1996-05-01), Petersen
patent: 5535406 (1996-07-01), Kolchinsky
patent: 5619665 (1997-04-01), Emma
patent: 5636224 (1997-06-01), Voith et al.
patent: 5652875 (1997-07-01), Taylor
patent: 5682493 (1997-10-01), Yung et al.
patent: 5684980 (1997-11-01), Casselman
patent: 5696956 (1997-12-01), Razdan et al.
patent: 5726584 (1998-03-01), Freidin
patent: 5742180 (1998-04-01), DeHon et al.
patent: 5784636 (1998-07-01), Rupp
patent: 5794062 (1998-08-01), Baxter
patent: 5819064 (1998-10-01), Razdan et al.
patent: 5822588 (1998-10-01), Sterling et al.
patent: 5828835 (1998-10-01), Isfeld et al.
patent: 5847578 (1998-12-01), Noakes et al.
patent: 5850564 (1998-12-01), Ting
patent: 5920202 (1999-07-01), Young et al.
patent: 5926036 (1999-07-01), Cliff et al.
patent: 5943150 (1999-08-01), Deri et al.
patent: 5956518 (1999-09-01), DeHon et al.
patent: 5963050 (1999-10-01), Young et al.
patent: 5977793 (1999-11-01), Reddy et al.
patent: 5982195 (1999-11-01), Cliff et al.
patent: 5986465 (1999-11-01), Mendel
patent: 5999734 (1999-12-01), Willis et al.
patent: 6026478 (2000-02-01), Dowling
patent: 6092174 (2000-07-01), Roussakov
patent: 6115580 (2000-09-01), Chuprun et al.
patent: 6167502 (2000-12-01), Pechanek
patent: 6219628 (2001-04-01), Kodosky et al.
patent: 6237079 (2001-05-01), Stoney
patent: 6292388 (2001-09-01), Camarota
patent: 6343337 (2002-01-01), Dubey
patent: 6353841 (2002-03-01), Marshall et al.
patent: 6374403 (2002-04-01), Darte
patent: 6393026 (2002-05-01), Irwin
patent: 6415424 (2002-07-01), Arimilli et al.
patent: 6418045 (2002-07-01), Camarota
patent: 6426648 (2002-07-01), Rupp
patent: 6467009 (2002-10-01), Winegarden
patent: 6505241 (2003-01-01), Pitts
patent: 6557092 (2003-04-01), Callen
patent: 6622233 (2003-09-01), Gilson
patent: 6633181 (2003-10-01), Rupp
patent: 6698015 (2004-02-01), Moberg et al.
patent: 6721866 (2004-04-01), Roussel
patent: 6721884 (2004-04-01), De Oliveira Kastrup Pereira et al.
patent: 6732354 (2004-05-01), Ebeling et al.
patent: 6744274 (2004-06-01), Arnold et al.
patent: 6795900 (2004-09-01), Miller et al.
patent: 6799236 (2004-09-01), Dice et al.
patent: 6817013 (2004-11-01), Tabata et al.
patent: 6831690 (2004-12-01), John
patent: 6857110 (2005-02-01), Rupp et al.
patent: 6874110 (2005-03-01), Camarota
patent: 6883084 (2005-04-01), Donohoe
patent: 6954845 (2005-10-01), Arnold et al.
patent: 6968544 (2005-11-01), Schneider
patent: 6986127 (2006-01-01), Newlin
patent: 6996709 (2006-02-01), Arnold
patent: 7000211 (2006-02-01), Arnold
patent: 7062520 (2006-06-01), Rupp
patent: 7086047 (2006-08-01), Edwards
patent: 7178062 (2007-02-01), Dice
patent: 7254142 (2007-08-01), Hagsand et al.
patent: 7269616 (2007-09-01), Rupp
patent: 7350054 (2008-03-01), Furuta
patent: 7373642 (2008-05-01), Williams
patent: 7412684 (2008-08-01), Gutberlet
patent: 2001/0049816 (2001-12-01), Rupp
patent: 2003/0097546 (2003-05-01), Taylor
patent: 2003/0108119 (2003-06-01), Mohebbi et al.
patent: 2003/0196058 (2003-10-01), Ramagopal et al.
patent: 2004/0019765 (2004-01-01), Klein, Jr.
patent: 2004/0193852 (2004-09-01), Johnson
patent: 2004/0208602 (2004-10-01), Plante
patent: 2005/0166038 (2005-07-01), Wang et al.
patent: 0 507 507 (1992-10-01), None
patent: 0 668 659 (1995-08-01), None
patent: 1 443 417 (2004-08-01), None
patent: 152355 (2002-07-01), None
patent: 152994 (2002-07-01), None
patent: 168210 (2003-04-01), None
Goldblatt, K., “The Low-Cost, Efficient Serial Configuration of Spartan FPGAs,” XAPPO98, Nov. 13, 1998 (Version 1.0), XILINX.
Scott, S. et al., “The Cray T3E Network: Adaptive Routing in a High Performance 3D Torus,” HOT Interconnects IV, Aug. 15-16, 1996, Stanford University.
Golestari, S.J., “A Stop-and-Go Queuing Framework for Congestion Management,” Aplications, Technologies, Architectures, and Protocols for Computer Communication, Proceedings of the ACM Symposium on Communications Architectures & Protocols, 1990, ACM Press, New York, NY USA.
Dally, W. et al., “Deadlock Free Message Routing in Mutliprocessor Interconnection Networks,” Computer Science Department, California Institute of Technology, May 10, 1985.
Garland, D. et al., “An Introduction to Software Architecture,” Advances in Software Engineering and Knowledge Engineering, 1993, vol. 1, World Scientific Publishing Company, New Jersey, USA.
Beeck et al., “CRISP: A Template for Reconfigurable Instruction Set Processors,” FPL 2001, LNCS 2147, pp. 296-305, Springer-Verlag Berlin Heidelberg, 2001.
Bechade et al., “Programmable Arithmetic/Logic Circuits,” IBM Technical Disclosure Bulletin, U.S. IBM Corp., New York, vol. 3, No. 11, Apr. 1981, pp. 4870-4873, XP-000713711.
DeHon, Andre, “Transit Note #118 Notes on Coupling Processors with Reconfigurable Logic,” M.I.T. Transit Project, Last Updated Mar. 21, 1995.
Tanenbaum, Andrew S., “Modern Operating Systems,” 2001, 2nd edition, Prentice Hall, New Jersey, p. 31.
Hennessy, John L. and David A. Patterson, “Computer Organization and Design: The Hardware/Software Interface,” 1998, 2nd edition, Morgan Kaufmann Publishers, Inc., San Francisco, CA, p. 345.
Lee, K.C.,. “A Virtual Bus Architecture for Dynamic Parallel Processing,” Feb. 1993, IEEE Transactions on Parallel and Undistributed Systems, vol. 4, No. 2, pp. 121-130.
Goldblatt, Kim, “The Low-Cost, Efficient Serial Configuration of Spartan FPGAs,” Nov. 13, 1998, XAPP098 (Version 1.0), XILINX.
Scott, Steven L. and Gregory M. Thorson, “The Cray T3E Network: Adaptive Routing in a High Performance 3D Torus,” Aug. 15-16, 1996, HOT Interconnects IV, Stanford University.
Golestani, S. Jamaloddin, “A Sto-and-Go Queuing Framework for Congestion Management,” 1990, Proc. of the ACM Symposium on Communications Architectures & Protocols, ACM Press, New York, NY, pp. 8-18.
Dally, William J. and Charles L. Seitz, “Deadlock Free Message Routing in Multiprocessor Interconnection Networks,” May 10, 1985, Computer Science Department, California Institute of Technology.
Garlan, David and Mary Shaw, “An Introduction to Software Architecture,” Jan. 1994, CMU-CS-94-166, School of Computer Science, Carnegie Mellon University, Pittsburgh, PA.
Intel and Hewlett-Packard, “IA-64 Application Instruction Set Architecture Guide

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