Configuring a communications system with a configurable data tra

Details Configuring a communications system with a configurable data tra Configuring a communications system with a configurable data tra

1997-12-01

2000-02-22

An, Meng-Ai T.

Electrical computers and digital processing systems: processing

Processing architecture

712 27, 712 28, 712 29, 712 32, 712 37, 712 40, 370331, 370338, G06F 1500

Patent

active

060292393

ABSTRACT:
A communications system utilizes an embedded Digital Signal Processor (DSP), a DSP interface and memory architecture, a micro-controller interface, a DSP operating system (OS), a data flow model, and an interface for hardware blocks. The design allows software to control much of the configuration of the architecture while using hardware to provide efficient data flow, signal processing, and memory access. In devices with embedded DSPs, memory access is often the bottleneck and is tightly coupled to the efficiency of the design. The platform architecture involves a method that allows the sharing of the DSP memory with other custom hardware blocks or the micro-controller. The DSP can operate at full millions-of-instructions-per-second (MIPS) while another function is transferring data to and from memory. This allows for an efficient use of the memory and for a partitioning of the DSP tasks between software and hardware.

REFERENCES:
patent: 5250940 (1993-10-01), Valentaten et al.
patent: 5315235 (1994-05-01), Atherton et al.
patent: 5581173 (1996-12-01), Yalla et al.
patent: 5631651 (1997-05-01), Nichols et al.
patent: 5790817 (1998-08-01), Asghar et al.

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