Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2011-02-22
2011-02-22
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S128000, C716S117000, C703S016000, C713S002000, C713S100000, C717S106000, C717S114000, C717S136000
Reexamination Certificate
active
07895558
ABSTRACT:
A method is disclosed of associating a mapping function with a configuration construct of a digital design defined by one or more hardware description language (HDL) files. According to the method, in the HDL files, a configuration latch is specified within a design entity forming at least a portion of the digital design. In addition, a Dial is specified that defines a relationship between each of a plurality of input values and a respective one of a plurality of different output values. The HDL files also include a statement that instantiates an instance of the Dial in association with the configuration latch such that a one-to-one correspondence exists between a value contained within the configuration latch and an input value of the instance of the Dial. The HDL files further include a statement associating the Dial with a mapping function that applies a selected transformation to values read from or written to the instance of the Dial.
REFERENCES:
patent: 7392501 (2008-06-01), Roesner et al.
patent: 2005/0149883 (2005-07-01), Roesner et al.
Roesner Wolfgang
Williams Derek Edward
Dillon & Yudell LLP
International Machines Corporation
Kik Phallaka
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