Configuration pin emulation circuit for a field programmable gat

Details Configuration pin emulation circuit for a field programmable gat Configuration pin emulation circuit for a field programmable gat

1996-09-17

1999-01-19

Teska, Kevin J.

G06F 9455, G06F 1750

Patent

active

058623655

ABSTRACT:
An integrated circuit for providing a pin-for-pin replacement of a field programmable gate array (FPGA). The integrated circuit includes an emulation circuit for mimicking the programmable stage (e.g., initialization, configuration and start-up states) of the FPGA. The integrated circuit is designed to be transparent to the user/customer, thereby eliminating the need for a costly redesign of a user's circuit board.

REFERENCES:
patent: 5276811 (1994-01-01), Zifferer et al.
patent: 5572710 (1996-11-01), Asano et al.
patent: 5581742 (1996-12-01), Lin et al.
The Programmable Logic Data Book; Xilinx, Inc.;.COPYRGT.1995; pp. 107 (and cover page).

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