Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Layout editor
Reexamination Certificate
2008-03-28
2011-11-22
Lin, Sun J (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Layout editor
C716S116000, C716S128000
Reexamination Certificate
active
08065653
ABSTRACT:
Techniques for configuring a programmable integrated circuit (IC) include determining design elements of the programmable integrated circuit that need to be configured prior to run-time operation of the programmable IC. A user interface provides for configuring one or more parameters for each of the determined design elements that need to be configured. Thereafter, the design elements are configured based on the one or more parameter values specified through the user interface.
REFERENCES:
patent: 5276739 (1994-01-01), Krokstad et al.
patent: 5408235 (1995-04-01), Doyle et al.
patent: 5625583 (1997-04-01), Hyatt
patent: 5652893 (1997-07-01), Ben-Meir et al.
patent: 5661433 (1997-08-01), LaRosa et al.
patent: 5728933 (1998-03-01), Schultz et al.
patent: 5801958 (1998-09-01), Dangelo et al.
patent: 5818736 (1998-10-01), Leibold
patent: 6035320 (2000-03-01), Kiriaki et al.
patent: 6167364 (2000-12-01), Stellenberg et al.
patent: 6216254 (2001-04-01), Pesce et al.
patent: 6321369 (2001-11-01), Heile et al.
patent: 6401230 (2002-06-01), Ahanessians et al.
patent: 6421817 (2002-07-01), Mohan et al.
patent: 6425109 (2002-07-01), Choukalos et al.
patent: 6460172 (2002-10-01), Insenser Farre et al.
patent: 6496969 (2002-12-01), Feng et al.
patent: 6546297 (2003-04-01), Gaston et al.
patent: 6556044 (2003-04-01), Langhammer et al.
patent: 6578174 (2003-06-01), Zizzo
patent: 6634009 (2003-10-01), Molson et al.
patent: 6636169 (2003-10-01), Distinti et al.
patent: 6671869 (2003-12-01), Davidson et al.
patent: 6703961 (2004-03-01), Mueck et al.
patent: 6715132 (2004-03-01), Bartz et al.
patent: 6725441 (2004-04-01), Keller et al.
patent: 6750876 (2004-06-01), Atsatt et al.
patent: 6961686 (2005-11-01), Kodosky et al.
patent: 7003732 (2006-02-01), Zhaksilikov
patent: 7082584 (2006-07-01), Lahner et al.
patent: 7086014 (2006-08-01), Bartz et al.
patent: 7100133 (2006-08-01), Meiyappan et al.
patent: 7100139 (2006-08-01), Anderson et al.
patent: 7113090 (2006-09-01), Saylor et al.
patent: 7143360 (2006-11-01), Ogami et al.
patent: 7299307 (2007-11-01), Early et al.
patent: 7337407 (2008-02-01), Ogami et al.
patent: 7392011 (2008-06-01), Jacomb-Hood
patent: 7437692 (2008-10-01), Oberlaender
patent: 7461274 (2008-12-01), Merkin
patent: 7809545 (2010-10-01), Ciofi et al.
patent: 2003/0086300 (2003-05-01), Noyes et al.
patent: 2008/0086668 (2008-04-01), Jefferson et al.
patent: 2008/0178143 (2008-07-01), Dougan et al.
patent: 2010/0023865 (2010-01-01), Fulker et al.
USPTO Non-Final Rejection for U.S. Appl. No. 12/058,534 dated Jan. 11, 2011; 17 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 12/004,833 dated Dec. 21, 2010; 8 pages.
USPTO Requirement Restriction for U.S. Appl. No. 12/004,833 dated Sep. 22, 2010; 6 pages.
Application No. 12/058,586; “System and Method for Monitoring a Target Device,” Kenneth Ogami et al. filed on Mar. 28, 2008; 56 pages.
USPTO Notice of Allowance for U.S. Appl. No. 10/118,682 dated Apr. 3, 2006; 4 pages.
USPTO Final Rejection for U.S. Appl. No. 10/118,682 dated Oct. 12, 2005; 11 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 10/118,682 dated Jun. 16, 2005; 12 pages.
USPTO Requirement Restriction for U.S. Appl. No. 10/118,682 dated Apr. 28, 2005; 4 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 10/118,682 dated Jan. 12, 2005; 11 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 10/118,682 dated Sep. 24, 2004; 8 pages.
USPTO Final Rejection for U.S. Appl. No. 10/118,682 dated May 3, 2004; 8 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 10/118,682 dated Feb. 25, 2004; 9 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 10/118,682 dated Nov. 3, 2003; 8 pages.
USPTO Notice of Allowance for U.S. Appl. No. 10/329,162 dated Jul. 5, 2007; 7 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 10/329,162 dated Jan. 29, 2007; 10 pages.
USPTO Final Rejection for U.S. Appl. No. 10/329,162 dated Aug. 25, 2006; 12 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 10/329,162 dated Mar. 10, 2006; 9 pages.
USPTO Final Rejection for U.S. Appl. No. 10/329,162 dated Sep. 21, 2005; 12 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 10/329,162 dated Apr. 21, 2005; 10 pages.
USPTO Advisory Action for U.S. Appl. No. 10/329,162 dated Mar. 29, 2005; 2 pages.
USPTO Final Rejection for U.S. Appl. No. 10/329,162 dated Dec. 15, 2004; 10 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 10/329,162 dated Aug. 2, 2004; 8 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 12/058,586 dated May 24, 2011; 13 pages.
USPTO Final Rejection for U.S. Appl. No. 12/058,534 dated Jun. 2, 2011; 15 pages.
USPTO Final Rejection for U.S. Appl. No. 12/004,833 dated May 25, 2011; 11 pages.
USPTO Notice of Allowance for U.S. Appl. No. 12/057,149 dated Mar. 17, 2011; 8 pages.
USPTO Notice of Allowance for U.S. Appl. No. 12/057,149 dated Nov. 30, 2010; 7 pages.
“PSoC Designer: Integrated Development Environment User Guide”; Jul. 17, 2001; Cypress MicroSystems; Revision 1.11; 109 pages.
Seguine et al.; “Layout Guidelines for PSoC CapSense”; Oct. 31, 2005; Cypress Perform; 15 pages.
Best Andrew
Ogami Kenneth
Zhaksilikov Marat
Cypress Semiconductor Corporation
Lin Sun J
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