Configuration of memory device

Details Configuration of memory device Configuration of memory device

2008-07-22

2008-07-22

Dinh, Son T (Department: 2824)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S189040, C365S233120

Reexamination Certificate

active

11393627

ABSTRACT:
In an improved construction of a memory device, the memory device includes a first group of pins via which a command/address signals are received and via which data signals are received, and a second group of pins via which the command/address signals are received and via which data signals are output. When the data signals are input to the first group of pins, the command/address signals are received via the second group of pins. When the data signals are output from the second group of pins, the command/address signals are received via the first group of pins.

REFERENCES:
patent: 5604710 (1997-02-01), Tomishima et al.
patent: 5982674 (1999-11-01), Lines et al.
patent: 6147924 (2000-11-01), Lee et al.
patent: 2004/0027857 (2004-02-01), Ooishi
patent: 2004/0133736 (2004-07-01), Kyung
patent: 07-262769 (1995-10-01), None
patent: 10-0188016 (1999-01-01), None
patent: 10-2004-0062717 (2004-09-01), None

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