Configuration of a metal insulator semiconductor with a processo

Details Configuration of a metal insulator semiconductor with a processo Configuration of a metal insulator semiconductor with a processo

1986-04-08

1988-03-01

Edlow, Martin H.

357 236, 357 26, 357 41, H01L 2714

Patent

active

047290030

ABSTRACT:
A method for fabricating a metal insulator semiconductor includes first forming a substrate (10) having an array of switching elements formed therein. A plurality of deformable Indium pads (16) and (18) are then formed on the surface of the substrate and in contact with each of the switching elements. A superstrate is formed from a layer of mercury cadmium telluride (32) and a layer of dielectric insulating material (34). The superstrate is pressed down adjacent the substrate (10) with the upper surface of the conductive gates (16) and (18) contracting the lower surface of the dielectric layer (34). The deformable pads (16) and (18) conform to the lower surface of the dielectric layer (34). Epoxy (36) is then disposed in the interstices of the device to provide an adhesive force between the substrate (10) and the superstrate. The thickness of the mercury cadmium telluride layer (32) is then decreased to reduce the path length for photon generated carriers created at the upper surface to diffuse to the diametrically opposite side.

REFERENCES:
patent: 4447291 (1984-05-01), Schulte

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