Reexamination Certificate
1997-12-22
2001-06-05
Beausoleil, Robert (Department: 2181)
Reexamination Certificate
active
06241400
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a computer and, more particularly, to a configuration register space in a peripheral component interface (“PCI”) compliant bus interface unit which can be selectively disconnected from a clocking signal to save power whenever the configuration space is not being accessed.
2. Description of the Related Art
Power consumption in an electronic device is always a significant concern. Longevity of the power supply, heat dissipation, physical size, weight, efficiency and other related characteristics are paramount in designing the electronic device. These characteristics become exceptionally critical when the device is a self-sufficient portable unit.
A portable unit is one in which power is supplied from a battery during times when the unit is decoupled from its main power source, e.g., a 110 volt ac supply. In some instances, the battery functions as an auxiliary power source to ensure critical circuits are kept alive and to retain information stored in memory. In other instances, the battery functions as the main power source to fully power the device in its operational state.
Various types of portable units can be powered from a battery including, for example, a computer. Modern portable computers are called upon to perform at increasingly higher levels. For example, a high performance portable computer may employ a high speed CPU and multiple buses between the CPU and numerous input/output devices. Multiple buses may include a CPU local bus connected directly to the CPU, a peripheral bus connected to slower input/output devices, and a mezzanine bus connected between the CPU local bus and the peripheral bus. The peripheral bus can be classified as, for example, an industry standard architecture (“ISA”) bus, and enhanced ISA (“EISA”) bus or a microchannel bus. The mezzanine bus can be classified as, for example, a peripheral component interface (“PCI”) bus to which higher speed input/output devices can be connected.
A bus interface unit is used to allow I/O and memory devices to communicate with the bus they reside on. A bridge is a device that connects two busses together. According to known terminology, the bus interface unit coupled between the CPU bus and the PCI bus is often termed the “north bridge”. Similarly, the bus interface unit between the PCI bus and the peripheral bus is often termed the “south bridge”.
Any PCI device bus interface unit contains a substantial amount of sequential logic. The sequential logic is clocked by a clocking signal either generated within the PCI device or forwarded to the PCI device. A substantial portion of the sequential logic is dedicated to latches and/or flip-flips within the PCI device attributed to an input/output address space, a memory address space and a configuration address space.
In each instance, the address spaces embodying latches and flip-flops define a set of registers which are clocked by the clocking signal. When clocked, the sequential logic consumes a substantial amount of power. This is especially profound when considering the high speed at which the north bridge must operate relative to a high speed CPU bus and PCI bus. When the computer is first powered on, reset or booted, configuration software scans the PCI bus, or busses, to determine what PCI devices exist and the particular configuration requirements of each device. This process is referred to as scanning, walking, probing, or enumerating the bus. In order to facilitate this operation, all PCI devices including the north bridge must implement a base set of configuration registers defined within the configuration address space. Accordingly, software drives initialization and configuration via a separate configuration address space containing a substantial amount of sequential logic clocked by the clocking signal. The PCI specification allocates a maximum of 256 addressable bytes for configuration purposes. Typically, a PCI device requires approximately 128 bytes of configuration registers for the purpose of configuration. Each register consumes power during configuration. However, clocks to those registers remain on even after configuration. Clocking the configuration space after configuration has ended unnecessarily consumes an exorbitant amount of power within the PCI device.
It would be desirable to produce a portable computer which can accommodate a PCI device with specific power management modes of operation. An improved PCI device is therefore needed which can selectively inhibit a clocking signal to a portion of sequential logic within the PCI device. Disconnecting or inhibiting the clocking signal must occur in a dynamic fashion to be an effective power management tool. Dynamic disconnect occurs to only portions of the sequential logic which are not called upon for operation. Thus, the improved power management mechanism takes into account times when configuration cycles on the PCI bus are running, enabled or disabled. When the configuration cycles are not currently running on the PCI bus or disabled, the improved power management mechanism advantageously inhibits power drain caused by clocking signals forwarded to the configuration address space within the PCI device. Reducing power within PCI devices would reduce the power consumption in high performance personal computers allowing additional functions to be added to the mobile PC.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by an improved power management techniques hereof. Power management involves reducing power in the PCI devices by disconnecting or inhibiting a clocking signal to a portion of the PCI device after configuration or initialization of the computer has ended. The first approach is specific to a north bridge. In the first approach a mechanism is used to monitor the CPU bus for accesses to a particular address location within the input/output address space of the CPU. When access to that space occurs, and when an enable flag is set within a register of that space, conversion or translation into a configuration access can occur upon the PCI bus. More specifically, by setting the enable flag or bit location to an enable value, a configuration cycle is generated upon the PCI bus and a configuration space (configuration registers) within the north bridge is clocked by the clocking signal. However, when the enable flag or bit location contains a value indicating a “disable” condition, configuration cannot occur regardless of whether the configuration address register within the input/output space of the processor is accessed. Absent configuration, the configuration space within the north bridge is disconnected or inhibited from receiving the clocking signal. Advantageously, the enable flag or value within the enable bit determines whether the clocking signal will clock the configuration space. If the enable flag or bit value is disabled, then power will not be consumed by at least a substantial portion of sequential logic residing within the configuration space.
Significant power savings within the north bridge can occur by monitoring accesses to the CPU input/output address space and, more particularly, by monitoring the enable flag or enable bit within a configuration address register within the input/output address space written to or modified by the CPU. Modification of the enable flag occurs either during a boot procedure, or possibly during subsequent procedures in which one or more PCI devices are re-configured. By writing an enable value to the enable flag, more PCI devices are re-configured. By writing an enable value to the enable flag, configuration or re-configuration of a PCI device can occur; however, writing a disable value to the enable flag or enable bit after configuration or re-configuration will disable future, inadvertent re-configurations. It is therefore desired that the enable flag be set (or enabled) only when configuration is desired and then disabled immediately thereafter. This can occur in software, or possibly through a time-out procedure. When disabl
Alzien Khaldoun
Melo Maria L.
Beausoleil Robert
Compaq Computer Corporation
Conley & Rose & Tayon P.C.
Daffer Kevin L.
Vo Tim
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