Configuration for multi-layer ball grid array

Details Configuration for multi-layer ball grid array Configuration for multi-layer ball grid array

2011-04-26

2011-04-26

Warren, Matthew E (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S698000, C257SE23011, C438S667000

Reexamination Certificate

active

07932604

ABSTRACT:
Disclosed herein is a method and circuit arrangement for a multi-layer ball grid array configuration. In one embodiment, there is presented a board comprising a first surface, a second surface, and a plurality of vias. The second surface is connected to the first surface. The plurality of vias are positioned to form a substantially straight line on the first surface. The plurality of vias comprises a first via and a second via. The first via is adjacent to the second via. The first via emerges on the second surface on one side of the substantially straight line. The second via emerges on another side of the substantially straight line.

REFERENCES:
patent: 3599091 (1971-08-01), Warner, Jr.
patent: 3917984 (1975-11-01), Kong et al.
patent: 5355283 (1994-10-01), Marrs et al.
patent: 5417578 (1995-05-01), Mroczkowski et al.
patent: 5489804 (1996-02-01), Pasch
patent: 6040622 (2000-03-01), Wallace
patent: 6245175 (2001-06-01), Hotta et al.
patent: 2004/0212073 (2004-10-01), Divakar et al.

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