Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-03-26
2004-02-17
Le, N. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
Reexamination Certificate
active
06693447
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to a configuration for identifying contact faults during the testing of integrated circuits with a multiplicity of pins which protrude from a housing of the integrated circuit and are connected to respective pads on a semiconductor body of the integrated circuit.
Integrated circuits such as, in particular, memory modules are subjected to a test with regard to their functionality in a tester before being incorporated in an apparatus, for example a personal computer. It is the case, however, especially in memory modules, such as SDRAMs, for example, that the majority of control inputs are active “low”, i.e. the control inputs are activated when a low potential or no potential is applied to them.
If contact problems arise in a tester or else in a “burn-in oven” such that contact is not made with all the desired pins, then circuits of pins with which contact has not been made in the integrated circuit can behave like activated circuits. This leads to incorrect measurement results especially in the case of the burn-in process.
Therefore, after passing through a testing unit, integrated circuits may be incorrectly classified as “pass” or completely satisfactory even though the integrated circuits in some instances contain faults and should be assessed as “fail”.
Thus, experiments have been carried out in which pins were disconnected or broken off from integrated circuits before the latter were introduced into a tester. Contact could not, of course, be made with the terminals with the broken-off pins in the tester. Nevertheless, a large number of such integrated circuits were assessed as “pass” since their control inputs with the broken-off pins are active “low” and, consequently, behave as if they were activated internally in the tester.
The above problems are aggravated in integrated circuits of so-called TSOP modules (TSOP=“Thin Small Outline Package”), that is to say in modules which are distinguished by a particularly planar form. This is probably due to the fact that as the miniaturization of the modules advances, the testing thereof imposes ever more stringent requirements. In order to surmount this difficulty, the following concept has already been conceived of, namely that of avoiding possible contact problems in the tester by testing the TSOP modules while still in the “unbent” state, that is to say by introducing the modules into the tester before the pins are prepared and shaped. Although better contact-making of the pins is inherently achieved as a result of this, a procedure of this type nonetheless requires special receptacles in the tester, which ultimately makes the test operation complicated and costly. In addition, it has been shown that even when the TSOP modules are tested with the pins in the unbent state, faults can occur, with the result that modules are allocated the assessment “pass” even though contact has not been made with all of the desired pins in the tester.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a configuration for identifying contact faults during the testing of integrated circuits that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which surmounts the above difficulties and reliably guarantees that the only integrated circuits which are classified as “good or pass” are those which have actually been checked for their functionality.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated circuit configuration for identifying contact faults during testing of the integrated circuit configuration: including: a semiconductor body; pads disposed on the semiconductor body; input buffers connected to the pads and defining a connection node between each respective pad and a respective input buffer; a housing protecting the semiconductor body; a multiplicity of pins protruding from the housing and connected to the pads; and a pull-up or pull-down device connected to the connection node between the respective pad and the respective input buffer, the pull-up or pull-down device holding the respective pad at a high or low potential by impressing a holding current if contact has not been made with a pin associated with the respective pad during testing resulting in avoiding activating a circuit section connected to the pin associated with the respective pad.
In the case of a configuration of the type mentioned in the introduction, the object is achieved according to the invention by the pull-up or pull-down devices connected between respective pads and the integrated circuit. The devices in each case hold the pads at a high or low potential by impressing a holding current, if contact has not been made with the associated pin during testing, with the result that activation of the circuit section connected to the pin is avoided.
The invention therefore takes a fundamentally different approach from that of the previous prior art. Instead of making further improvements to the tester itself or implementing measures which enable reliable contact to be made with the pins by the tester, the testing is undertaken by a pull-up or pull-down device incorporated in the integrated circuit. Thus, a pull-up device pulls up the potential at the pins with which contact has not been made, with the result that these pins, which are inherently active “low”, are no longer assessed as activated. Even if, therefore, contact has not been made with a number of pins in the tester, it is ensured that the potential of the pins is raised, so that the pins change from the activated state to the inactivate state during the test operation. In other words activation of the connected circuit is avoided. The pull-down device operates in a manner of “mirror-inverted” with respect to the pull-up device. It pulls the potential at a pad connected to a pin with which contact has not been made to a low value, thereby avoiding activation of the connected circuit, which is otherwise activated at a high potential.
Modules in which pads connected to pins with which contact has not been made are held at a high or low potential by the pull-up or pull-down device are straightforwardly identified as “fail” in the tester, so that the quality of the pass modules is reliably ensured.
As is known, the input leakage specification (input leakage current specification) of module inputs is very narrow and is currently in the region of ±1 &mgr;A in the case of SDRAMs compared with ±10 &mgr;A in the case of standard EDO DRAMs. A “bleeder” at each input pad is virtually impossible therefore, because the maximum leakage currents tolerated by customers is in the region of 10 nA. Therefore, the pull-up or pull-down device is in a first active state during the test mode or burn-in mode and/or during the switch-on phase of the module. The current capacity of the device is chosen to be large enough that undesired switching of input circuits which are connected to the relevant pad and with which contact has not been made is reliably avoided, but without the function of the module being disrupted. During normal operation, the pull-up or pull-down device is either completely switched off or in a second active state, its current capacity being lower than in the first state and being dimensioned in such a way that the normal function of the module is not adversely affected and, in a computer system, the sum of the input leakage currents does not exceed a tenable amount.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a configuration for identifying contact faults during the testing of integrated circuits, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
REFERE
Savignac Dominique
Weber Frank
Wirth Norbert
Greenberg Laurence A.
Kerveros James
Le N.
Locher Ralph E.
Siemens Aktiengesellschaft
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