Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2001-06-11
2004-04-27
Nguyen, Linh M. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C375S374000
Reexamination Certificate
active
06727738
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to delay locked loops used to provide accurate synchronization in a system operating in synchronization with a clock, semiconductor devices including the delay locked loops, and control methods for systems operating in synchronization with a clock.
2. Description of the Background Art
A case is considered in which in a system operating in synchronization with a clock a component receives a read instruction in synchronization with a clock that instructs reading data and in response to the instruction the read data is returned to a system bus in synchronization with a clock. Note that hereinafter a reference character ADR denotes a binary code, a reference character ADR<k> means a k-th bit in a binary code, referred to as a register value ADR<k> or a binary code ADR<k>.
It is also assumed that with a system clock period represented by “T” the component requires a time period T0 to prepare read data after it has received the read instruction, and that clock period T may be greater in length than period T0 or vice versa and for an integer N there is established a relationship N×T<T0<(N+1)×T. In this scenario, the following manner is considered to provide an output.
With reference to
FIG. 17
, at time t1 (a rising edge
0
of a clock CLKext) a read instruction to read data is issued in synchronization with clock CLKext, and read data is prepared, and in synchronization with a subsequent rising edge
1
of clock CLKext (at time t2: t2=t1+T) the data is output.
The component requires a time period Td after it has received clock CLKext and before it outputs prepared data to an output buffer. As such, the data is actually output when time period Td elapses following the clock edge
1
.
Time period Td includes, as shown in
FIG. 18
, a time period Tin and a time period Tout (Td=Tin+Tout). Time period Tin is required for the component to internally generate from clock CLKext a clock CLKin driving the output buffer. Time period Tout is required for driving a system bus corresponding to an output load after clock CLKin has driven and thus started the output buffer to operate until the system bus exceeds a predetermined logical threshold value.
As such, in this system it is not until Td elapses following clock edge
1
that data is actually output to a system bus. Accordingly, the system is designed to take data in at subsequent clock edge
2
.
If in such an operation, system clock period T is equal to or smaller than Td and thus has a high frequency, then a problem occurs, as shown in FIG.
19
. In
FIG. 19
, at clock edge
1
a data output operation is started, and at clock edge
2
data is not yet transmitted on a bus, since delay time Td is greater than T. As such, it is not until a subsequent clock edge
3
arrives that the system can take data in. In other words, if the system is designed to take data in at clock edge
2
the system would operate erroneously.
In particular, a recently developed memory, DDR-SDRAM (double data rate, synchronous dynamic random access memory) outputs data at both of rising edge and trailing edge of a clock. As such, if the aforementioned method of outputting data is applied to the DDR-SDRAM, as shown in
FIG. 20
, the same problem as described above would come to the surface at a time point when half the clock period is substantially equal to Td.
Such a disadvantage as above is conventionally overcome by a delay locked loop (hereinafter referred to as a DLL). With reference to
FIG. 21
, a component employing a DLL receives a system clock CLKext and internally delays the clock via a delay element by Tdll1. Then it generates an internal clock CLKin2 rising before a rising edge of the system clock by a time period corresponding to an output buffer drive time (Tout′=Tout).
Using internal clock CLKin2 to drive the output buffer allows read data to have been output on a bus at an edge of system clock CLKext. That is, a relation Tdll1+Tout′=m×T, wherein m is an integer equal to or larger than one, can be established.
Thus a DLL can be used to time an output in synchronization with a clock. The DLL can also be similarly used for an input buffer allowing a component to take in various control signals and input data through a system bus.
The operating timing of an input buffer which does not use a DLL will be described with reference to FIG.
22
. As shown in
FIG. 22
, this input buffer without DLL requires a time period Tin after clock CLKext is received and before a component internally generates internal clock CLKin.
As such, an externally received control signal SIG is internally delayed by a time period Tin″ corresponding to Tin, to be a signal SIGin. At the edge timing of internal clock CLKin, signal SIGin is latched by a latch circuit
910
and ascertained. In the figure an ascertained control signal is shown.
With reference to
FIG. 23
, latch circuit
910
includes inverters IV
1
-IV
4
and NAND circuits N
1
-N
4
. Inverters IV
1
and IV
3
operate in response to internal clock CLKin and a clock/CLKin, an inverted version of internal clock CLKin.
As such, if a DLL is not used, it is not until a delay of at least Tin elapses following an edge of system clock CLKext that a component can use a control signal. As such, the component itself would not be suitable for high speed operation.
Such delay is compensated for by the aforementioned DLL. Reference will now be made to
FIG. 24
to describe an operating waveform when the DLL is used. With reference to
FIG. 24
, system clock CLKext is delayed in a component via a delay element by Tdll2 to generate an internal clock CLKin3 having an edge at the same position at that of a system clock CLKext. If internal clock CLKin3 is used to latch control signal SIG then control signal SIG can be latched faster than the above case by a time period corresponding to Tin. Thus the system can be designed to be suitable for high speed operation. Herein, from the above description there can be established a relationship Tdll12=m×T.
Reference will now be made to
FIG. 25
to describe by way of example a configuration of a circuit configuring a DLL conventionally used. A conventional DLL 9000, as shown in
FIG. 25
, includes a clock buffer
1
, a fine delay element
3
, a coarse delay element
5
, a decoder
70
, a binary counter
80
corresponding to a delay register, a phase comparator
9
, a timing clock generator
10
, a pulse generator
11
and a replica circuit
13
.
External clock CLKext is input to clock buffer
1
. Clock buffer
1
outputs a clock BUFFCLK. Between external clock CLKext and clock BUFFCLK time Tin elapses.
Clock BUFFCLK is input to fine delay element
3
. Fine delay element
3
delays clock BUFFCLK by Tfine to output a clock CLKA. Delay time Tfine, elapsing between clock BUFFCLK and clock CLKA, is variable, varying in a small unit Tf (a unit of approximately 40 psec) depending on the value of a 3-bit register value ADR<0:2> input to fine delay element
3
.
Clock CLKA is input to coarse delay element
5
. Coarse delay element
5
delays clock CLKA by Tcoarse to output a clock CLKB. Delay time Tcoarse, elapsing between clocks CLKA and CLKB, is variable, varying in a coarse unit Tc depending on a 6-bit register value ADR<3:8>. It should be noted that Tc is set to be 8 times Tf in length.
Fine delay element
3
and coarse delay element
5
each provide an amount of delay determined by a register value output from binary counter
80
.
In the circuit configuration, at least a delay time Tx is required for a clock to pass through fine delay element
3
and coarse delay element
5
. With the clock passing through fine delay element
3
and coarse delay element
5
, a delay of Tx would be inevitably result even if a register value is the value of a minimal delay time.
The conventional DLL has fine delay element
3
and coarse delay element
5
each having a delay time set by a binary code. For examp
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