Pulse or digital communications – Synchronizers
Patent
1993-09-17
1995-05-23
Chin, Stephen
Pulse or digital communications
Synchronizers
327156, 327141, 327291, 331 57, 326 93, H04L 702
Patent
active
054188229
ABSTRACT:
A configuration generates a clock signal from a digital signal by evaluating signal edges of the digital signal. A first device generates a pulse at a signal edge oriented in a first direction, and a second device generates a pulse at a signal edge oriented in a second direction being opposite the first direction. Each of the devices has one terminal for receiving a digital signal and one output. A voltage-controlled, triggerable oscillator device has at least two trigger inputs, one control input and one output. Each of the trigger inputs is connected to the output of a respective one of the first and second devices, and the output of the oscillator device is an output for the clock signal. An integration device has an input connected to the output of the oscillator device and has an output connected to the control input of the oscillator device.
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Patent Abstract of Japan Publ. No. JP 3076446, (Yoshida Hiroshi), Jun. 21, 1991.
IBM Technical Disclosure Bulletin No. 10, Mar. 1987, pp. 4427-4428, "Clock Recovery Phase-Locked Loop".
Mihai Banu, (IEEE) "MOS Oscillators with Multi-Decade Tuning Range and Gigahertz Maximum Speed".
Damianoff Wanjo
Schlachter Hans-Heiner
Chin Stephen
Greenberg Laurence A.
Lerner Herbert L.
Siemens Aktiengesellschaft
Tse Young
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