Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-08-02
2003-04-15
Karlsen, Ernest (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S754090
Reexamination Certificate
active
06549028
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to an arrangement and a method for testing a multiplicity of semiconductor chips at the wafer level, in which test signals are applied to the semiconductor chips, which have bonding pads, by a tester device.
In order to satisfy requisite quality requirements, it is known for semiconductor chips to be tested repeatedly during their fabrication. In this case, the semiconductor chips are fabricated in such a way that, from one wafer, several hundred or even several thousand semiconductor chips are formed in parallel with one another. In other words, up to several thousand semiconductor chips are thus produced from a single semiconductor wafer.
The preferred material for the semiconductor wafers is silicon. However, it is also possible to use other materials, such as gallium arsenide for example.
Of the plurality of tests mentioned, what is tested in a first test is, for example, whether the semiconductor chips are all functional. This first test makes use of the fact that all the chips to be tested are still combined in the wafer. In other words, at least this test is performed at the wafer level.
If non-functional semiconductor chips or semiconductor chips having an inadequate operating behavior are detected during this first test, then these semiconductor chips are not completed any further, in order thereby to keep the fabrication costs of the semiconductor chips from the wafer as low as possible.
The test equipment required for carrying out the tests at the wafer level is extremely cost-intensive. This is due to the fact that as the complexity of the semiconductor chips increases, that is to say as the storage capacity rises in the case of semiconductor memories, for example, the test times become longer, so that ultimately, owing to the proportionality between test time and memory area size in the case of semiconductor memories, the test costs grow practically exponentially with each new generation of memories.
In order to prevent these test costs from rising to an excessively great extent, attempts have been made heretofore to test the greatest possible number of semiconductor chips in parallel with one another at the wafer level. For this purpose, special probe cards (PCBS) are used, containing a multiplicity of probe needles with which, by way of example, each time the probe card is lowered onto the wafer, eight or sixteen test units or DUTs (“Device Under Test”) can be tested in parallel. In this case, one DUT may comprise a plurality of semiconductor chips.
In order, then, to completely test all the semiconductor chips on a wafer, it is necessary to perform a plurality of lowering operations with the probe cards. It goes without saying that each time the probe cards are lowered, an extremely precise positional relationship between probe card and wafer has to be adhered to since the probe needles each have to impinge on special bonding pads of the semiconductor chips. It should be noted here that a probe card can contain several hundred probe needles and the bonding pads have lateral dimensions of the order of magnitude of approximately 100 &mgr;m.
On account of this high number of probe needles per probe card and the precise alignment demanded between probe needles and bonding pads, the probe cards are inherently already extremely complex. The complexity for the probe cards is additionally increased by the fact that they cannot be used generally, since they have to be configured in a product-specific manner:
if a new product is present in the form of a new semiconductor chip, then the probe card has to be adapted to the bonding pads thereof. This applies even when, for example, the dimensions of an existing semiconductor chip are reduced.
For the reasons mentioned, therefore, existing tester devices are very complicated and extremely costly.
As the diameter of the wafers increases from, for example, 6 inches through 8 inches up to 12 inches and with decreasing structure dimensions or higher integration levels, the number of semiconductor chips per wafer rises tremendously. The number of probe needles per probe card cannot be increased arbitrarily. Therefore, the tests have to be performed sequentially with the existing tester devices at the wafer level, which likewise causes a considerable increase in the test times and thus also in the test costs.
In order to keep these test times and test costs somewhat under control, the tester devices have hitherto been continuously refined and improved. Nevertheless, a suitable solution has not yet been found to the problem of continuously lengthening test times associated with rising test costs.
SUMMARY OF THE INVENTION
The object of the present invention, therefore, is to provide an arrangement and a method for testing a multiplicity of semiconductor chips at the wafer level such that practically all the semiconductor chips or at least a large number thereof on the wafer can be tested in parallel in a simple manner.
In the case of an arrangement or a method of the type mentioned in the introduction, this object is achieved according to the invention by virtue of the fact that an intermediate wiring plane, which can be connected to the tester device, with at least one global test bus for at least a plurality of semiconductor chips and/or at least one test pad with an area for the semiconductor chips which is larger than the area of the bonding pads is provided on the semiconductor wafer.
The invention thus enables an arrangement and a method with which, as required, even all the semiconductor chips on a wafer can be tested in parallel with one another. This is made possible by the additionally provided intermediate wiring plane or layer which is applied to the semiconductor wafer that is processed in this respect, and which serves as a compact interface to the external tester device. On account of this intermediate wiring plane, the previous equipment such as, in particular, probe cards, etc., which must be assigned to each individual type of semiconductor chips, is no longer necessary. After the test has been carried out at the wafer level, the intermediate wiring plane can readily be removed since it is no longer required. Afterwards, the wafer can then be divided into the individual semiconductor chips.
As has already been mentioned above, the intermediate wiring plane comprises a test bus and/or, if appropriate, a plurality of test pads. In this case, the test bus extends over the entire wafer, with the result that, via said test bus, all the required input signals and output signals can be passed to the individual semiconductor chips and, respectively, picked off from said semiconductor chips. The test pads may be distributed over the entire wafer. In contrast to the bonding pads, these test pads can be made much larger, so that they allow simple contact with the tester device.
To form the intermediate wiring plane, it is possible to use any technology that is suitable for this purpose. However, care should be taken to ensure that the required structure size remains in the region of the lateral dimensions of the bonding pads in order that contact can be reliably made with the latter via said intermediate wiring plane. A suitable technology for producing the intermediate wiring plane may be, for example, the use of conductive polymers which are printed onto the surface of the wafer or are patterned by photolithography. Once the test has been carried out, the intermediate wiring plane can then be removed simply using a suitable solvent.
The invention thus treads a completely different path from the previous prior art: instead of further refinement of needle cards, a separate intermediate wiring plane is applied to the wafer and it serves solely for test purposes and is removed again after the tests have been carried out. A series of advantages can thus be obtained which cannot be achieved by the prior art:
All the semiconductor chips of a wafer can be tested in parallel with one another. On account of the global test bus, it is unnecessary for con
Greenberg Laurence A.
Infineon - Technologies AG
Karlsen Ernest
Locher Ralph E.
Stemer Werner H.
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