Configuration and method for testing a delay chain within a micr

Details Configuration and method for testing a delay chain within a micr Configuration and method for testing a delay chain within a micr

1994-03-11

1995-07-04

Wambach, Margaret Rose

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

327276, 327277, 327294, 324527, H03H 1126, H03K 104

Patent

active

054303940

ABSTRACT:
A test configuration is provided which allows a plurality of variable delay units within a delay chain of a microprocessor clock generator to be compared with respect to one another. During normal operation, a set of multiplexers interposed within the delay chain are configured such that the plurality of variable delay units are electrically coupled in series with respect to one another. An external command signal may be provided to the microprocessor to initiate a test operation in which the variable delay units are tested for possible defects. During the test operation, a control unit selects the multiplexers such that the four delay units are electrically separated from one another. A common test signal is then driven through two or more of the variable delay units simultaneously, and a compare circuit coupled to the output of each variable delay unit determines whether a transition in the common pulse signal propagated through each variable delay unit at essentially the same time. If no manufacturing defects are present, the four outputs of the variable delay units should be virtually indistinguishable from one another. The results of the compare operation may be driven on external pins of the microprocessor or may be processed internally within the microprocessor. Similar tests may be conducted throughout the entire operating range of the variable delay units.

REFERENCES:
patent: 4414637 (1983-11-01), Stanley
patent: 5180937 (1993-01-01), Laird et al.

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