Configurable video output channel architecture

Details Configurable video output channel architecture Configurable video output channel architecture

1993-12-22

1997-06-10

Peng, John K.

Television

Image signal processing circuitry specific to television

Gray scale transformation

348181, 348682, 348689, H04N 557, H04N 1700, H04N 552, H04N 518

Patent

active

056381379

ABSTRACT:
A configurable video output channel architecture includes a plurality of parallel video pipelines arranged to drive a video display; a device for selecting an output of one of the video pipelines and generating a readback signal representative thereof; and a device for adjusting a display specification of at least one of the video pipelines using the readback signal. The display specification adjusted may include the maximum video level, the blanking level, and the sync level of the video waveform. The adjusting device may also adjust the characteristic impedance of each pipeline. The selecting device includes a multiplexer and an analog to digital converter, and the adjusting device includes a controller which monitors the readback signal and generates a control signal to adjust the display specification if the readback signal is outside of a desired range.

REFERENCES:
patent: 4011587 (1977-03-01), Arter et al.
Computer Design, vol. 23, No. 13, Nov. 1984, Littleton, MA, R.R. Castleberry, "High Spped D-A Converters Yield Precision Graphics".

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