Configurable row decoder driver circuit

Details Configurable row decoder driver circuit Configurable row decoder driver circuit

1992-01-13

1993-02-16

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307463, H03K 1901

Patent

active

051873940

ABSTRACT:
A configurable decode circuit for decoding in a block architected SRAM. The configurable decode circuit comprising a decode circuit (10) which decodes through a process of deselection, a first buffer circuit (12) for buffering decode circuit (10), a delayed clock signal (15) for enabling first buffer circuit (12), a gated transmission means (13) for decoupling first buffer circuit from second buffer circuit (14), second buffer circuit (14) for driving capacitive loads, and a means for delaying driver output (16) for enabling gated transmission means (13). The decode circuit (10) is built for simplifying synthesis of the layout of a configurable decode circuit for varying configurations. The configurable decode optimizes performance by reducing the number of circuits in the critical delay path and minimizing capacitive loading on internal circuit nodes.

REFERENCES:
patent: 4491748 (1985-01-01), Chappell et al.
patent: 4567581 (1986-01-01), Dumbri et al.
patent: 4725743 (1986-08-01), Anderson
patent: 4798977 (1989-01-01), Sakui et al.
patent: 5118972 (1992-06-01), Wissel et al.
O'Connor, "Row-Address-Decoder-Driver Circuit", U.S. Statutory Invention Registration H97, Aug. 5, 1986.

Affiliated with

Also associated with

Rating

Configurable row decoder driver circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Configurable row decoder driver circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Configurable row decoder driver circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2149899