Configurable power segmentation using a nanotube structure

Active solid-state devices (e.g. – transistors – solid-state diode – Organic semiconductor material

Reexamination Certificate

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C257S368000, C438S599000

Reexamination Certificate

active

07847285

ABSTRACT:
Configurable power segmentation using a nanotube structure is disclosed. In one embodiment, a method includes patterning a nanotube structure adjacent to a transistor layer in an integrated circuit, and coupling a power region in the transistor layer to at least one power source based on a state of the nanotube structure. Nanotube material may be sputtered over a plurality of layers to form the nanotube structure. The nanotube structure may be curved to flex to a conductive surface when a current is applied to the nanotube structure. The power region may be coupled with at least two power sources that are concatenated together to provide cascaded current to the power region. One or more power regions in the integrated circuit may be enable based on the patterning the nanotube structure and the coupling of the power region to at least one power source.

REFERENCES:
patent: 2003/0022428 (2003-01-01), Segal et al.
Poseidon joins LSI Logic RapidChip Platform ASIC Partner Program, providing performance analysis and acceleration for ARM-based designs; http://www.design-reuse.com
ews/?id=1.

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