Configurable packet processor

Details Configurable packet processor Configurable packet processor

2007-06-26

2007-06-26

Vu, Huy D. (Department: 2616)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S397000, C370S474000

Reexamination Certificate

active

09988939

ABSTRACT:
A packet processing device has an on-board match engine memory. Actions to be taken on a packet can be looked up in the match engine memory using a key comprising a match engine index and a protocol field from the packet. The match engine index is obtained from either a relatively small on-board parser memory or a larger context memory. The parser memory contains match engine indices for sparse protocols. Performance approaching that of hard-wired packet processors can be obtained. New protocols or changes in protocols can be accommodated by writing new values into the match engine, parser and context memories. The packet processing device can be provided in a pipelined architecture.

REFERENCES:
patent: 6289414 (2001-09-01), Feldmeier et al.
patent: 6775284 (2004-08-01), Calvignac et al.
patent: 6904057 (2005-06-01), Sarkinen et al.
patent: 2002/0163935 (2002-11-01), Paatela et al.
patent: 2003/0007489 (2003-01-01), Krishnan et al.
patent: 2003/0079040 (2003-04-01), Jain et al.
patent: 2004/0208122 (2004-10-01), McDysan
patent: WO 01/48975 (2001-07-01), None

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