Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
2007-06-26
2007-06-26
Treat, William M. (Department: 2181)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
active
09751747
ABSTRACT:
An interface for transferring data between a central processing unit (CPU) and a plurality of coprocessors is provided. The interface includes an instruction bus and a data bus. The instruction bus is configured to transfer instructions to the plurality of coprocessors in an instruction transfer order, where particular instructions designate and direct one of the plurality of coprocessors to transfer the data to/from the CPU. The data bus is configured to subsequently transfer the data. Data order signals within the data bus prescribe a data transfer order that differs from the instruction transfer order by prescribing a transfer corresponding to a specific outstanding particular instruction, where the data transfer order is relative to outstanding instructions. The outstanding instructions are those of the particular instructions transferred to the one of the plurality of coprocessors that have not completed a data transfer.
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Hudepohl Lawrence Henry
Jones Darren Miller
Thekkath Radhika
Treue Franz
Huffman James W.
Huffman Richard K.
Mips Technologies, Inc.
Treat William M.
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