Configurable multiport memory interface

Details Configurable multiport memory interface Configurable multiport memory interface

1990-07-30

1995-04-18

Elmore, Reba I.

Boots, shoes, and leggings

395275, 3649674, G06F 1318

Patent

active

054086272

ABSTRACT:
The present invention uses a logic control to determine which of a plurality of processors receives priority, and generates WAIT signals for the non-selected processor. Further, user configurable pins exist that allow the user to determine the priority that the attached processor will obtain when simultaneous chip selects are transmitted.

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