Configurable memory block

Details Configurable memory block Configurable memory block

2000-10-17

2001-10-02

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230030

Reexamination Certificate

active

06298005

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to memories generally and, more particularly, to an embedded memory that may be configured to operate in a number of modes.
BACKGROUND OF THE INVENTION
Conventional embedded memory devices are typically synchronous in nature. A synchronous design, such as a synchronous SRAM, will not generally consume current when the clock to the block is not switching. Such designs, when implemented in embedded memories, are typically implemented with a fixed word-width.
One disadvantage with such a conventional approach is that it is not as flexible as a truly asynchronous device, which can be configured to operate either asynchronously or synchronously. For example, an asynchronous SRAM can be used to implement a logic function by using the address inputs as the logic function inputs, the data output(s) as the logic function output(s), and the memory bits as a lookup table for the output values for a given set of input values.
SUMMARY OF THE INVENTION
The present invention concerns a circuit and method comprising a memory and a plurality of address circuits. The memory array may comprise a plurality of storage elements each configured to read and write data in response to an internal address signal. The plurality of address circuits may each be configured to generate one of said internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) a control signal.
The objects, features and advantages of the present invention include providing a memory block that may be configured to operate having (i) asynchronous inputs and outputs, (ii) synchronous inputs (e.g., synchronous flowthrough), (iii) synchronous outputs, (iv) synchronous inputs and outputs (e.g., pipelined), (v) a number of bit widths (e.g., x32, x16, x8, x4, x2, x1), (vi) a Read Only Memory (ROM) mode, and/or (vii) a mode implementing a logic function.


REFERENCES:
patent: 5384745 (1995-01-01), Konishi et al.
patent: 5835970 (1998-11-01), Landry et al.
patent: 6134181 (2000-10-01), Laundry

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