Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
Reexamination Certificate
1999-02-10
2002-09-17
Coleman, Eric (Department: 2783)
Electrical computers and digital processing systems: processing
Processing architecture
Long instruction word
C717S152000
Reexamination Certificate
active
06453407
ABSTRACT:
FIELD AND BACKGROUND OF THE INVENTION
The present invention relates to data processor architecture and, more particularly, to data processor architecture for digital signal processing.
The term “digital signal processing” (DSP) herein denotes any data processing procedures which operate on digital representations of data, particularly, but not limited to, those which represent analog signals or quantities. Hereinafter, the terms “digital signal processor” and “processor” both denote any device which is capable of processing digital data, including, but not limited to, representations of analog signals or quantities.
Digital signal processing algorithms, such as the Fast Fourier Transform (FFT), usually involve complex and intensive computation. Moreover, many DSP applications must run in real time, so a processor's ability to handle a large number of calculations in a short amount of time is of fundamental importance. It is also important that programs for the processor be easy to code and maintain. Furthermore, system power consumption is important for many DSP applications which require low power drain, for example to maximize battery life in cellular phone handsets, laptop computers, and consumer audio equipment. Thus, there are three aspects of a digital signal processor which influence the overall performance of a system based thereon. The first is the program execution speed, the second is the ease of programming, and the third is the power consumption during execution of the program code. In typical applications of digital signal processing, one or more of these aspects are critical.
Execution speed is highly dependent on the extent of parallel processing employed by the processor during program execution. The terms “parallel processing” and “parallel” denote the execution of a plurality of data operations substantially simultaneously. When comparing two processors with the same clock rate, if the first is capable of performing two instructions in parallel (per cycle), while the second is capable of executing only one instruction per cycle, then the first processor has a clear advantage, because if all other conditions are identical, the first processor will execute a program in half the time required by the second processor.
Ease of programming is also vitally important, since the nature of the instruction set has a major influence on the suitability of a processor for different tasks. Today's processors must provide an instruction set that has the properties of flexibility and orthogonality. Flexibility assures that dependencies between instructions are reduced to minimum, thus allowing the programmer to write code freely, without restrictions. Orthogonality frees the programmer from concern over which operands are permitted in the current operation, because orthogonality permits most operands to be used in most instructions. Thus, flexibility and orthogonality in an instruction set reduce the restrictions and hence reduce the burden on the programmer.
Power consumption is dependent on the hardware complexity of the processor, such as the width of data buses, the number of computation units employed, and the number of instruction decoders necessary to handle the different fields in an instruction word.
There are currently two “mainstream” architectures for digital signal processors. Both involve design compromises concerning the three issues mentioned above. The first mainstream architecture is referred to as the “regular” architecture, and is characterized by the execution of a single instruction in a machine cycle. The second mainstream architecture is referred to as the “Very Long Instruction Word” (VLIW) architecture, and is characterized by the execution of several instructions in a single machine cycle. An overview of the prior art can be obtained from DSP Processor Fundamentals—Architectures and Features, by Lapsley, Bier, Shohan, and Lee, Berkeley Design Technology, Inc., 1996., and from some of the technical literature pertaining to currently-available digital signal processors, such as the Texas Instruments “C
6
” series. Technical documentation provided by the manufacturer for this series of digital signal processors includes the TMS320C62xx CPUand Instruction Set, July 1997, Texas Instruments Incorporated, Houston, Tex. A discussion of the architecture of this digital signal processor is found in “The VelociTI Architecture of the TMS320C6x” by Thomas J. Dillon, Jr., in The Proceedings of the 8
th
International Conference on Signal Processing Applications & Technology, pp. 838-842, September, 1997, Miller Freeman, Inc., San Francisco, Calif.
A regular processor, where a single instruction is executed per machine cycle, features a relatively small program data bus, because it is necessary to fetch only one instruction word (typically 32 bits wide) per cycle. In addition, since only one instruction is executed per machine cycle, the number of computation units in the execution unit of the processor is small (typically
2
—an adder and a multiplier). As noted above, the program bus width and the number of computation units directly influence the power consumption of the processor. Thus, the regular architecture is also characterized by a relatively low power consumption. It is also easier to write program code for a regular processor than for a VLIW processor. The inherent disadvantage of the regular architecture is that the execution speed (usually measured in “MIPS”, or Million-Instructions executed Per Second) is smaller than that of the VLIW architecture described below.
The second mainstream architecture, the VLIW architecture, implements an instruction set in which a number of simple, noninterdependent operations are packed into the same instruction word. The term “instruction word” herein denotes a set of instructions contained in a single programming step, such that at run-time, the processor executes all the instructions within the instruction word in parallel. Thus, the VLIW architecture requires a plurality of computation units in the processor, along with a corresponding plurality of instruction decoders to analyze the instructions contained in the instruction word fetched from the program memory. VLIW architecture has the advantage of parallel processing, thus increasing the MIPS capability of the processor. VLIW architecture, however, also requires wider memory banks, multiple computation units, and multiple instruction decoders, thus increasing chip area and power consumption. In addition, the skills required of the programmer to write code for a VLIW architecture processor are also inherently higher, in order to exploit the parallel processing capabilities of the processor.
There is thus a widely recognized need for a processor architecture which combines the advantages of the regular architecture and the VLIW architecture, while reducing or eliminating the disadvantages inherent in these two mainstream architectures. It would be highly advantageous to have a processor which has a high execution speed, ease of programming, and low power consumption. These goals are met by the present invention.
SUMMARY OF THE INVENTION
The configurable long instruction word (CLIW) architecture described here is an innovative processor architecture and instruction set design which optimizes processing speed, ease of programming, and power consumption to benefit DSP programming. The present invention combines the advantages of both the regular and VLIW architectures in a flexible design which overcomes the limitations of the current technologies. In a CLIW processor, several instructions may be executed in parallel during a single cycle without the need for an enlarged general program memory bus, and without the need for multiple processor instruction decoders to support the parallel instruction execution. The present invention also represents improvements in the ease of programming, both from the standpoint of the instruction set as well as the syntax of the instructions themselves.
The general concept of the present invention may be better understoo
Blum Rivka
Cohen Elliot
Granot Haim
Hershko Anat
Knuth Robert
Coleman Eric
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
LandOfFree
Configurable long instruction word architecture and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Configurable long instruction word architecture and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Configurable long instruction word architecture and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2882702